JPS6464200A - Memory address control circuit - Google Patents
Memory address control circuitInfo
- Publication number
- JPS6464200A JPS6464200A JP62222431A JP22243187A JPS6464200A JP S6464200 A JPS6464200 A JP S6464200A JP 62222431 A JP62222431 A JP 62222431A JP 22243187 A JP22243187 A JP 22243187A JP S6464200 A JPS6464200 A JP S6464200A
- Authority
- JP
- Japan
- Prior art keywords
- writing
- reading
- outputs
- address
- executed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To attain writing and reading in a block unit at all address areas and to shorten a test time by adding an OR circuit being inputted by a control signal to set a special address area and the output signal of the prescribed bit of a program counter. CONSTITUTION:When a special address 30 of an EPROM 10 is written and read, control signals 12 and 13 are 'O,' and the output of OR outputs 35 and 36 is the logical level of outputs 3 and 4 of a program counter 9 as it is. Consequently, when outputs 1- 4 are (0000), an output 14 of a decoder 11 is an 'H,' and an area 30 is designated. Each time counter outputs 1- 4 are increased, the 'H' is outputted to signals 15-17, an address is updated and writing is executed. At the time of completing writing, the counter 9 is returned to an initial condition and reading is successively executed. By the change of address signals 1-4, the writing and reading are successively executed to areas 31-33. Thus, the writing and reading can be executed at a block unit and therefore, the discovery of the defective place is hastened and a testing time is shortened.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62222431A JPH0793039B2 (en) | 1987-09-04 | 1987-09-04 | Memory address control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62222431A JPH0793039B2 (en) | 1987-09-04 | 1987-09-04 | Memory address control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6464200A true JPS6464200A (en) | 1989-03-10 |
| JPH0793039B2 JPH0793039B2 (en) | 1995-10-09 |
Family
ID=16782288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62222431A Expired - Lifetime JPH0793039B2 (en) | 1987-09-04 | 1987-09-04 | Memory address control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793039B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100396700B1 (en) * | 2001-04-02 | 2003-09-03 | 주식회사 하이닉스반도체 | test circuit |
-
1987
- 1987-09-04 JP JP62222431A patent/JPH0793039B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100396700B1 (en) * | 2001-04-02 | 2003-09-03 | 주식회사 하이닉스반도체 | test circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0793039B2 (en) | 1995-10-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |