JPS55122298A - Memory test method - Google Patents
Memory test methodInfo
- Publication number
- JPS55122298A JPS55122298A JP2779579A JP2779579A JPS55122298A JP S55122298 A JPS55122298 A JP S55122298A JP 2779579 A JP2779579 A JP 2779579A JP 2779579 A JP2779579 A JP 2779579A JP S55122298 A JPS55122298 A JP S55122298A
- Authority
- JP
- Japan
- Prior art keywords
- cells
- cell
- logical
- information
- diagonal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE: To make it possible to test surely the influence upon semi-selected cells, by writing different logics to one cell and another cell on a diagonal line of a square matrix constitution and by reading and deciding them.
CONSTITUTION: Logical 0 is written to all cells of tested memory circuit 3 having a square matrix constitution by driving memory driving circuit 2. Next, logical 1 is written onto a cell on the diagonal, and information of a cell in the same line or column as this cell is outputted to signal line 7, and it is decided whether this cell is left written or not by control circuit 1. This operation is performed for all cells on this diagonal line. Next, information of all cells of circuit 3 are read, and it is decided whether all cells on the diagonal line above hold logical 1 or not and other cells hold logical 0 or not. Next, the write logical value for cells on the diagonal line and other cells is inverted to perform three steps above. Thus, it is decided whether information of cells agree with prescribed logical values each time information is outputted to signal line 7.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2779579A JPS55122298A (en) | 1979-03-09 | 1979-03-09 | Memory test method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2779579A JPS55122298A (en) | 1979-03-09 | 1979-03-09 | Memory test method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55122298A true JPS55122298A (en) | 1980-09-19 |
Family
ID=12230901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2779579A Pending JPS55122298A (en) | 1979-03-09 | 1979-03-09 | Memory test method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55122298A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS646776A (en) * | 1987-06-29 | 1989-01-11 | Nippon Telegraph & Telephone | Method of testing semiconductor memory |
JPH01150873A (en) * | 1987-12-07 | 1989-06-13 | Sharp Corp | Testing method for semiconductor storage device |
KR100387014B1 (en) * | 2000-05-19 | 2003-06-12 | 가부시키가이샤 아드반테스트 | Semiconductor testing device |
-
1979
- 1979-03-09 JP JP2779579A patent/JPS55122298A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS646776A (en) * | 1987-06-29 | 1989-01-11 | Nippon Telegraph & Telephone | Method of testing semiconductor memory |
JPH01150873A (en) * | 1987-12-07 | 1989-06-13 | Sharp Corp | Testing method for semiconductor storage device |
KR100387014B1 (en) * | 2000-05-19 | 2003-06-12 | 가부시키가이샤 아드반테스트 | Semiconductor testing device |
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