JPS5587396A - Memory test system - Google Patents
Memory test systemInfo
- Publication number
- JPS5587396A JPS5587396A JP16039878A JP16039878A JPS5587396A JP S5587396 A JPS5587396 A JP S5587396A JP 16039878 A JP16039878 A JP 16039878A JP 16039878 A JP16039878 A JP 16039878A JP S5587396 A JPS5587396 A JP S5587396A
- Authority
- JP
- Japan
- Prior art keywords
- data
- address
- writing
- bit
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To secure the easy and accurate detection for the fault of the address- related circuit of the memory device by writing the data after selection of the address bit and then comparing the writing data with the reading data.
CONSTITUTION: Address bit A0 is selected based on the address designation information, and writing data WD is set to logic 0. Then the writing address is varied in sequence to write the data into all addresses of tested device 1, and then the reading address is varied in sequence to read out all data. Under the normal state of both bit A0 and the memory cell, data WD and modified reading data RD' become identical to each other. After this test, bit A0 is selected along with data WD set to logic 1 to carry out the writing and reading in the same way. And then a comparison is given between the both data, and the normalcy is confirmed for the address line A0 and the memory cell when the coincidence is obtained through the comparison.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16039878A JPS5587396A (en) | 1978-12-25 | 1978-12-25 | Memory test system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16039878A JPS5587396A (en) | 1978-12-25 | 1978-12-25 | Memory test system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5587396A true JPS5587396A (en) | 1980-07-02 |
JPS6130356B2 JPS6130356B2 (en) | 1986-07-12 |
Family
ID=15714074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16039878A Granted JPS5587396A (en) | 1978-12-25 | 1978-12-25 | Memory test system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5587396A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59191197A (en) * | 1983-04-12 | 1984-10-30 | Usac Electronics Ind Co Ltd | Memory tester |
-
1978
- 1978-12-25 JP JP16039878A patent/JPS5587396A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59191197A (en) * | 1983-04-12 | 1984-10-30 | Usac Electronics Ind Co Ltd | Memory tester |
Also Published As
Publication number | Publication date |
---|---|
JPS6130356B2 (en) | 1986-07-12 |
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