JPS5587396A - Memory test system - Google Patents

Memory test system

Info

Publication number
JPS5587396A
JPS5587396A JP16039878A JP16039878A JPS5587396A JP S5587396 A JPS5587396 A JP S5587396A JP 16039878 A JP16039878 A JP 16039878A JP 16039878 A JP16039878 A JP 16039878A JP S5587396 A JPS5587396 A JP S5587396A
Authority
JP
Japan
Prior art keywords
data
address
writing
bit
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16039878A
Other languages
Japanese (ja)
Other versions
JPS6130356B2 (en
Inventor
Tatsuo Kadoma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Usac Electronic Ind Co Ltd
Original Assignee
Usac Electronic Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Usac Electronic Ind Co Ltd filed Critical Usac Electronic Ind Co Ltd
Priority to JP16039878A priority Critical patent/JPS5587396A/en
Publication of JPS5587396A publication Critical patent/JPS5587396A/en
Publication of JPS6130356B2 publication Critical patent/JPS6130356B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To secure the easy and accurate detection for the fault of the address- related circuit of the memory device by writing the data after selection of the address bit and then comparing the writing data with the reading data.
CONSTITUTION: Address bit A0 is selected based on the address designation information, and writing data WD is set to logic 0. Then the writing address is varied in sequence to write the data into all addresses of tested device 1, and then the reading address is varied in sequence to read out all data. Under the normal state of both bit A0 and the memory cell, data WD and modified reading data RD' become identical to each other. After this test, bit A0 is selected along with data WD set to logic 1 to carry out the writing and reading in the same way. And then a comparison is given between the both data, and the normalcy is confirmed for the address line A0 and the memory cell when the coincidence is obtained through the comparison.
COPYRIGHT: (C)1980,JPO&Japio
JP16039878A 1978-12-25 1978-12-25 Memory test system Granted JPS5587396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16039878A JPS5587396A (en) 1978-12-25 1978-12-25 Memory test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16039878A JPS5587396A (en) 1978-12-25 1978-12-25 Memory test system

Publications (2)

Publication Number Publication Date
JPS5587396A true JPS5587396A (en) 1980-07-02
JPS6130356B2 JPS6130356B2 (en) 1986-07-12

Family

ID=15714074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16039878A Granted JPS5587396A (en) 1978-12-25 1978-12-25 Memory test system

Country Status (1)

Country Link
JP (1) JPS5587396A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59191197A (en) * 1983-04-12 1984-10-30 Usac Electronics Ind Co Ltd Memory tester

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59191197A (en) * 1983-04-12 1984-10-30 Usac Electronics Ind Co Ltd Memory tester

Also Published As

Publication number Publication date
JPS6130356B2 (en) 1986-07-12

Similar Documents

Publication Publication Date Title
HK167795A (en) Integrated semiconductor store with parallel test facility and redundancy process
EP0193210A3 (en) Semiconductor memory device with a built-in test circuit
JPS57111893A (en) Relieving system of defective memory
JPS5587396A (en) Memory test system
JPS573298A (en) Memory integrated circuit
JPS55163697A (en) Memory device
JPS5320823A (en) Memory unit test system
JPS5590000A (en) Error detection system for memory
JPS5683900A (en) Buffer recording device
JPS5558896A (en) Analyzer for memory defect
JPS5654698A (en) Test method of memory device
JPS5712498A (en) Integrated circuit device for memory
JPS57120283A (en) Cash memory control system
JPS5452946A (en) Semiconductor element
JPS56159747A (en) Program testing device
JPS5744296A (en) Storage device
JPS5528501A (en) Test system for memory device
JPS56107400A (en) Memory test device
JPS5637899A (en) Memory malfunction detection system
JPS5654695A (en) Associative memory device
JPS5447446A (en) Magnetic disc control unit
JPS54122945A (en) Memory circuit
JPS5677976A (en) Magnetic bubble memory chip
JPS5661100A (en) Error information collecting system
JPS55108996A (en) Memory test system