JPH01150873A - Testing method for semiconductor storage device - Google Patents

Abstract

PURPOSE:To efficiently execute a test without deteriorating failure detecting capacity by writing a checker board pattern in all memory cells, converting the data of the memory cell of a diagonal line to '1' and reading out the data which has been written in cell line and rows in the X direction and the Y direction to which each memory cell on the diagonal line belongs in this state. CONSTITUTION:First of all, a checker board pattern in which '0' and '1' are stored alternately is written in all memory cells. Subsequently, a data 1 is written in a memory cell (i, i) on one diagonal line of a memory cell matrix. Next, data which have been written in memory cell rows and lines in the X direction and the Y direction to which the memory cell (i, i) on the diagonal line belongs are read out alternately, while returning to an origin. In this state, by advancing successively this (i) to (N<1/2>-1) from '0', the memory cell is tested.

Description

[Detailed description of the invention] Industrial application fields The present invention relates to a method for testing a semiconductor memory device.

<Prior Art> With remarkable progress in semiconductor manufacturing technology, integrated circuits are becoming more dense and highly reliable, and there is a particular trend in storage capacity.

Semiconductor memory devices manufactured using such advanced technology are tested to see if the memory cells can perform a predetermined function at the end of the manufacturing process.

For testing, the NY or N2 system test method is adopted, in which 0 or 1 is written over the entire surface as a test pattern. In other words, the total storage capacity is N pi) C# line x F line]
When the basic N test pattern is moved in the row (or column) direction and tested, an NX&=N'' pattern is obtained.

<Problems to be Solved by the Invention> A test was conducted by applying the above-mentioned N2 or N2-based test method to a semiconductor memory device consisting of N memory cells.
In case c, more complex tests are possible than in the N-based test method, but the required test time increases exponentially, making it impractical for large-capacity semiconductor storage devices.

The present invention has been made in view of the above-mentioned problems, and provides a method for testing semiconductor memory devices that improves test efficiency without reducing defect detection ability.

Means for Solving Problems> The present invention writes a checkerboard pattern to all memory cells in a semiconductor memory device consisting of N-bit memory cells, then converts data in diagonal memory cells to 1, and In this state, starting from each memory cell on the diagonal line, data written in cell rows and columns in the X and Y directions to which the memory cell belongs is read out to test all memory cells.

Function> The present invention applies to a semiconductor memory device consisting of N bits (J1 rows x 5 columns), in which data 1 is stored equally in a checker board pattern in which data 0 and 1 are stored alternately, and in memory cells on the diagonal. By using the diagonal pattern to be written, by simply performing the basic N test pattern, there is no need to move in the row (or column) direction, and the N2 test pattern can be converted to the N test pattern. .

<Example> FIG. 1 schematically shows a DRAM in which N memory cells (J rows x J columns) are arranged in an xY force direction matrix. As the first step in testing a matrix semiconductor memory device, a checker board pattern in which data 0.1 appears alternately is written on the entire surface. Next, the memory cells located on one diagonal of the memory matrix (
For i, i), the written data is converted to 1.

For the semiconductor memory device into which the checkerboard pattern and diagonal pattern have been written, written data is sequentially read out to detect defective memory cells. That is, the second
As shown in the flowchart in the figure, the data written in the memory cell at address (0, 0) is read, and then the data in the memory cell at address (0, 1) located in the Y direction is read. Next, the data in the memory cell at address (0,0) is read again, and then the data in the memory cell at address (1,0) located in the X direction is read and the process returns to address (0,0). Similarly, the memory of address (0, i) located in the same Y direction and address (i, 0) (i = 1 to tp - 1) located in the same Y direction starting from address (0, 0) The data of each memory cell is sequentially read out, and the data of each memory cell is compared with a preset expected value to detect a defective memory cell.

After completing the test of the memory cells belonging to the row and column starting at address (0,0), move the starting point to the memory cell at address (1°1), and test the memory cell (1,i) in the Y direction and the memory cell (1,i) in the X direction. For memory cell (i, 1) (i=2~J''W-1), memory cell (1) on the diagonal line is
, 1), the memory cells in the Y direction and the X direction are sequentially and alternately read and inspected. Set the memory cell as the starting point (
By moving up to fW-1, goo1) and executing a similar test operation, N memory cells can be tested for defects.

That is, starting from a diagonal memory cell, memory cells in the X and Y directions to which the same memory cell belongs are sequentially read and tested, thereby performing an N-system test on a semiconductor memory device consisting of N memory cells. can be tested as a law.

<Effects of the Invention> As described above, according to the present invention, it is possible to change the N2 test pattern to the N test pattern, thereby reducing the time required for testing, and in particular, improving the efficiency of testing for DRAMs whose capacity is increasing. can.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram in which a test pattern is written according to an embodiment of the present invention, and FIG. 2 is a flow yard for explaining the test procedure of the embodiment.

Claims (1)

[Claims] 1. A method for testing a semiconductor memory device in which memory cells are arranged in an The process of writing data 1 to the memory cell (i, i) on one diagonal of the cell matrix, and the process of writing data 1 to the memory cell (i, i) on the diagonal, and
The data written in the memory cell columns and rows in the direction are read out alternately while returning from the memory cell (i, i) as the starting point, and the data written in the memory cell columns and rows in the direction are sequentially read from the memory cell (i, i) from 0 to (√(N)-1). 1. A method for testing a semiconductor memory device, characterized by testing memory cells in advance.