JPS59228726A - Malfunction analyzer - Google Patents

Abstract

PURPOSE:To analyze the processing steps which become the cause of an improper quality and to dfficiently manufacture a wafer by recording the positions on an article to be processed of a malfunction discovered during inspection of the steps at the respective steps, and comparing the recorded defect position with the improper position obtained by a test. CONSTITUTION:A plurality of malfunction inspecting units A1-An are provided on a malfunction analyzer, and disposed in response to n-Si gas phase growing step, surface oxidizing step, lithographic step (K), ion implantation step..., metal film forming step and electrode forming step. Defects on the wafer in the respective steps by the units A1-An are detected by the positions in X-Y coordinates, and the defect positions are recorded in the first memory M1. The position of the malfunction of the improper article is outputted at the quality tester P of property testing step (j), and recorded in the second memory M2. The defect position and the improper quality are compared by a computer C to analyze the cause of the improper quality, thereby improving the quality of the wafer.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a defect analysis technology, and in particular to a technology for analyzing which process is the cause of a quality defect in a product that has undergone a plurality of processing steps. This invention relates to techniques that are effective for use in the wafer manufacturing process in the manufacturing process.

[Background Art] Since semiconductor devices are required to have extremely high reliability, various defect inspections are performed in the semiconductor device manufacturing process, particularly in the wafer manufacturing process.

However, it is not clear whether defects discovered in each process will cause fatal characteristic defects, and defects are removed in each process as needed.

Therefore, if a characteristic defect is discovered in a wafer characteristic test after the wafer manufacturing process, even if the defect that causes this characteristic defect was discovered in the defect inspection of each process, this defect and the process cannot know. In particular, the present inventors have found that for defects that cannot be recognized from the appearance, such as impurity doping defects, it is extremely difficult to analyze which processing process caused the defect. It was done.

[Object of the Invention] An object of the present invention is to provide a defect analysis technique that can analyze processing steps that cause quality defects in products that have undergone a plurality of processing steps.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, the positions of defects found during the processing process on the object to be processed are categorized and recorded for each processing process, and the position of the defect on the product is recognized during the product quality test, and the recorded defect position is recorded. By comparing the position of the defect and the position of the defect obtained in the test to determine the corresponding position, it is assumed that the defect at that position caused the quality defect, and the cause of the quality defect in the process where the defect was discovered is determined. The analysis is performed to determine that there is a high possibility of the existence of

[Embodiment] FIG. 1 is a block diagram showing a failure analysis device which is an embodiment of the present invention, and FIGS. 2 and 3 are plan views for explaining the operation.

In this embodiment, this defect analysis device is configured to analyze which processing process causes the characteristic defect in the process of manufacturing semiconductor devices. )

This defect analysis device is equipped with a plurality of defect inspection devices A1 to An, and the defect inspection device is, for example, capable of optically detecting defects such as foreign matter attached to the processing surface of the wafer or formed scratches. The apparatus is configured to inspect the appearance of the wafer and output the position of the detected defect on the wafer U expressed in XY coordinates relative to the reference origin O of the wafer as shown in FIG. 2, for example. has been done. These defect inspection apparatuses A1 to An perform the process of vapor-phase growth of an n-5i layer on the surface of the sea urchin 1\, the process of oxidizing the surface of the n-8iH, the process of forming a pattern on the surface of the wafer, and the process of forming a pattern on the surface of the wafer. Each wafer λ is used in the process of implanting ions, producing metal films to form electrodes, forming electrode patterns, etc.
In the treatment process, the apparatus is connected to a device that specifically executes these processes, such as a CVD device, an oxidation furnace, an air pinner, an aligner, a developing device, a dry etching device, an ion implantation device, a film forming device, and the like.

Each of the defect inspection devices A1 to An is connected to a first storage device M1 as a recording means, and this storage device M1 is equipped with a magnetic recording medium etc. It is configured to classify defect positions on the same wafer for each processing device and store them cumulatively.

On the other hand, a wafer prober P performs various characteristic tests on a wafer as a processed product (hereinafter referred to as a product wafer). The wafer prober P, for example, contacts the electrode pads of each group of pellets on a product wafer with a probe needle and applies a predetermined test signal to detect pellets with defective characteristics, or even when the pellets are memory devices. The defective bits in the defective pellets are searched, and the positions of the detected defective pellets and defective bits on the product wafer Ua are expressed and output as XY markers relative to the reference origin 0, as shown in FIG. It is composed of

A second storage device M2 having a magnetic recording medium etc. is connected to this wafer prober P.
is configured to memorize the defective position on the product wafer.

The first and second storage devices M1 and M2 are connected to a computer C serving as a storage data comparison means, and this computer C determines whether the defective position is overlapped on the same wafer based on the storage data from both storage devices M1 and M2. It is configured to determine defects and read data regarding the defects and defects.

Next, the action will be explained.

For example, each defect inspection device A1 to An detects defects F1, F2, F4, F6, F7 in a group of processing devices in each process.
When defects are found at various positions on the same wafer U as shown in FIG. 2, the first storage device M1 stores the defects in the following manner so that each defect accumulates on the same wafer.

Defect F1...CVD equipment for n-3t vapor phase growth process,
Foreign object, position (xl, yl) on wafer U.

Defect F2: oxidation furnace, foreign matter, position (F2, F2) of the first surface oxidation step.

Defect F4: Aligner, scratch, position (F4, y+) at the level of the first lithography.

Defect F6: Dry etching device, scratch, position (xe, ys) of the first lithography layer.

Defect F7 ... Implantation device, foreign object, position (F7, F7
).

As a result of a characteristic test carried out by the wafer blower P in the characteristic test process on the product wafer Ua shown in FIG. When characteristic defects are found in each of the bits B1, B4, and B7 of the pellet at the positions shown in the figure, the second storage device M2 stores these defects in the following manner.

Bit B1...Poor resistance value, position (xl, yl)/bin) 134...Poor resistance value, position (F4, F4
)・Beep)B7...Poor pressure resistance, location (F7, F7).

Computer C stores data stored in first storage device M1;
Based on the data stored in the second storage device M2, defect data and defective data of the same processing target wafer U and product wafer Ua are compared. As a result of this comparison, if a defect and a defect overlap at the same position on the wafer, data regarding them are read out and displayed on an appropriate display means.

In the embodiment described above, the positions of the defective bits B1, B4, and B7 match the positions of the defective bits F1, F4, and F7, so that the stored data regarding these bits is read out.

For example, by examining the data regarding the defective bit B1 and the defect F1, it is possible to estimate the possibility that foreign matter attached in the CVD apparatus caused the sheet resistance defect.

By examining the data regarding defective bit B4 and defect F4, it is possible to estimate the possibility that foreign matter adhering to the aligner caused the defective Bakun line width.

Based on such estimation, it is possible to analyze processing steps in which defects that are likely to cause fatal defects occur in product wafers. Based on this analysis, measures to improve yield can be quickly taken.

[Effect (1): For each processing step, the position of the defect in the object to be processed is stored cumulatively, the position of the defective product is recognized through a quality test, and the defect position is compared with the defective position. By finding the positions where they overlap with each other, it is possible to discover defects corresponding to defects, so it is possible to quickly and automatically analyze processing steps in which defects that are likely to cause fatal defects occur.

(2) By comparing the defect position and the defective position and determining the position where they overlap with each other, it is possible to analyze the processing process in which defects that are likely to cause fatal defects occur, which is an important point in yield improvement measures. This makes it possible to start production earlier by shortening the countermeasure period.

(3) By using a computer to compare the defective position and the defective position and find the position where they overlap with each other, the analysis process can be performed more quickly.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, it is also possible to omit the second storage device and perform analysis in real time.

When using a computer or storage device, for example, record the location of defects in each process by drilling a dummy hole in the sheet-like object, and similarly record the location of defects found during quality tests. hole in another sheet at the location of
Coincident perforations may be determined by polymerizing both sheets.

The structure of the defect inspection device is arbitrary, and it is not necessarily provided in all processing steps.

The structure of the quality testing device is arbitrary, and the test items are not limited to electrical characteristics.

[Field of Application] The above explanation has mainly been about the application of the invention made by the present inventor to failure analysis of wafer processing in the manufacturing process of semiconductor devices, which is the field of application that formed the background of the invention, but the invention is not limited to this. It can be applied to failure analysis of products that are processed through multiple processes, rather than products that are processed through multiple processes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams for explaining the operation. A1 to An...defect inspection device, P...wafer prober, (quality testing device), Ml...first storage device (recording means), M2...second storage device, C...computer , U...Wafer (object to be processed), Ua...Product wafer (processed product), F1-Fn...Defect, 81-
Bn...Defective bit. Figure 1 Figure 1 Figure 2 Figure 3 A

Claims (1)

[Claims] 1. An inspection device that inspects an object to be processed in a plurality of processing steps and outputs the position of a defect on the object, and a record that records the position of a defect on the object for each processing step using this output. means, a testing device that tests the quality of the processed product and outputs the position of a quality defect in the product, and compares this quality defect position data with defect position data for each processing step of the recording means to find a match. What is claimed is: 1. A defect analysis device, comprising a comparison means for determining a position, and is configured to analyze a processing step that causes a quality defect. 2. The failure analysis device according to claim 1, wherein the recording means is comprised of a storage device, and the comparison device is comprised of a computer.