JPH1116973A - Manufacturing method of semiconductor device and semiconductor device manufactured therethrough - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly find out processes where lots of defectives occur by a method wherein the process conditions of the processes where lots of defectives occur are controlled. SOLUTION: The type, process name, and lot number of a wafer to be monitored by each inspection equipment are initially set. The wafer is introduced, a foreign objects attached to the wafer are detected by an inspection equipment A after the wafer is subjected to a process N81, and the wafer is subjected to a simplified probe check with an inspection equipment C without delay. Then, after the wafer is subjected to a process M82, the external defects of the wafer are detected, and the wafer is subjected to a simplified probe check with the inspection equipment C at once. With the progress of processes, the calculation of correlations among the check devices is automatically carried out at a regular interval, and when the calculated correlations exceeds the previously set thresholds, the process conditions of the processes are regulated again so as to keep the wafer high in yield. The check of each chip of the wafer by the bit as an object of check is carried out the same as above, and the correlations are compared with each other by the bit, so that data are increased in volume, and the checks are improved in reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer with a high yield, a manufacturing management system, and a semiconductor device manufactured by the method.

[0002]

2. Description of the Related Art In the manufacture of semiconductor wafers, which are becoming finer and have a more complicated circuit structure year by year, it has become a major issue how to secure a higher yield in a short period of time after the start of the manufacture.

[0003] Factors that reduce the yield are:
(1) Foreign matter and appearance defects (including abnormal crystal growth, disconnection, short-circuit, chipping, etc.), (2) Pattern formation defects (pattern width defects, etc.) due to misalignment, defocus, abnormal film thickness, abnormal etching, etc. ) Etc. exist. In mass production of semiconductor wafers, these defects are discrete.
(One failure occurs once every few wafers in the manufacture of semiconductor wafers) or continuously (one failure occurs once every several wafers in the manufacture of semiconductor wafers).

Conventionally, in order to avoid such discrete defects or continuous defects, a method has been adopted in which inspection is performed in a main process during manufacturing, defects are found, and countermeasures are taken.

[0005] For example, foreign matter inspection is disclosed in Japanese Patent Application Laid-Open No. 55-149829.
And Japanese Patent Application Laid-Open No. 59-65428 disclose a number of methods for detecting minute foreign matter present on an electronic component on which a pattern such as a semiconductor wafer is formed. Various inspection apparatuses employing these detection methods have been developed and used in production lines.
000 (Hitachi Electronics Engineering Co., Ltd. product catalog issued in November 1994) can analyze inspection data.

[0006]

Therefore, the problems to be solved by the present invention will be described by taking, as an example, the inspection of foreign substances on wafers, the inspection of appearance defects, and the inspection of probes.

The same wafer is inspected by a foreign substance inspection apparatus, an external defect inspection apparatus, and a probe inspection apparatus, and the coordinates of the detected foreign substance and external defect and the probe inspection result (perfect non-defective product, remedy non-defective product, defective product) in chip units are obtained. When the defect distribution map is created based on the original data, the result is as shown by 101a in FIG. 2, 101b in FIG. 3, and 101c in FIG. When the three defect distribution maps are compared (superimposed) and checked, the defect 102a, 102 of the foreign matter and the appearance defect detected by both the foreign matter inspection device and the appearance defect inspection device.
b. It is possible to know the defects 103a and 103b of foreign matters and appearance defects that could only be detected by the apparatus alone, and the defects 104a and 104b of foreign matters and appearance defects that could not be detected by the apparatus.

Therefore, when a Venn diagram is created based on the data obtained after checking the defect distribution maps of the detection results of the foreign matter inspection device and the probe inspection device, and the appearance defect inspection device and the probe inspection device, FIG. Become like
Here, if the detection method of each inspection device is different, FIGS.
As shown in 104a and 104b, there is a difference in the detection rate of a minute foreign matter or a defect of an appearance defect, which is just before the detection sensitivity. As a result, even if the inspection is performed by introducing the inspection apparatus, in some cases, the occurrence of a fatal defect that becomes a probe inspection defect may be overlooked, and a large number of defects may be allowed.
Therefore, it is an important issue how to quickly find a process in which many defects such as foreign matter and appearance defects that lead to a probe inspection failure occur and take countermeasures, in order to quickly achieve a high yield.

Until now, the matching (superposition) of the defect distribution map of the foreign substance inspection or the appearance defect inspection with the defect distribution map of the probe inspection has been performed by a production line engineer based on intuition and experience. Since the inspection process is performed only in the process and the lot, it has been a major factor obstructing the promotion of automation of the management of the inspection process.

An object of the present invention is to provide a manufacturing method capable of securing a high yield by providing a means for early searching for a process in which a large number of foreign matters and appearance defects are linked to probe inspection failures in the manufacture of semiconductor wafers. Another object of the present invention is to provide a manufacturing management system having this function and a high-yield semiconductor wafer manufactured by the manufacturing method.

[0011]

SUMMARY OF THE INVENTION The above object is achieved by a means for performing a foreign substance inspection, a means for performing a simple probe inspection such as disconnection or short-circuiting immediately after the foreign substance inspection, a defect distribution map of the foreign substance inspection apparatus, and a simple probe inspection apparatus. Means for determining the correlation of the defect distribution map, means for performing an external defect inspection, means for performing a simple probe inspection device such as a disconnection or short circuit immediately after the external defect inspection, a defect distribution map of the external defect inspection device, and a simple probe inspection device Means to find the correlation of the defect distribution map of the inspection equipment, means to find out the process where many defects such as foreign matter and appearance defects that lead to probe inspection failure occur based on the correlation of the defect distribution map of each inspection device, and failure of the process where many fatal defects occur A means for performing a mode analysis, a means for adjusting a process condition value of the step of generating a large number of defects based on an analysis result of the means, and a group of these inspection apparatuses It can be solved by providing a manufacturing method having a system for managing.

More specifically, in a semiconductor device manufacturing line including a plurality of processing steps, a semiconductor device of a specific type having undergone a predetermined processing step is subjected to a predetermined number of inspection apparatuses having different performances and detection methods. By performing a sampling inspection or a 100% inspection at a frequency and performing a simple probe inspection immediately thereafter, the degree of correlation of the failure distribution map of each inspection device is continuously monitored almost at the same time, and the production status is managed and grasped.

More preferably, the semiconductor devices of a plurality of types introduced into the processing step are subjected to sampling inspection or 100% inspection at a predetermined frequency by the plurality of inspection devices. The degree of correlation of the failure distribution map is continuously monitored, and the production status is managed and grasped.

In this case, the process condition value of the step of generating a large number of defects may be adjusted based on the degree of correlation of the defect distribution map of each inspection device for each type so that the total number of defects generated in all types is minimized. .

When the production line is managed with the probe inspection apparatus fixed after the completion of all processing steps as in the prior art, the inspection time is shifted up to about two months, and the specific failure mode confirmed by the probe inspection changes. Could be.
Even if it is determined that the inspection is normal (satisfies the management standard) based on the inspection result of the probe inspection apparatus, there are many cases where a foreign matter defect or an appearance defect defect actually occurs at that time.

The present invention has been made in consideration of such a situation, and quickly responds to a change in a failure occurrence mode by performing a simple probe inspection immediately after each inspection apparatus. In addition, by adjusting the process condition values of the large number of failure occurrence steps so that the total number of failure occurrences of all the kinds is minimized from the correlation degree of the failure distribution map of each inspection device for each kind, the semiconductor device can be efficiently manufactured. Can be manufactured.

FIG. 1 illustrates the concept of the present invention.

The inspection will be described by taking as an example the inspection of a defect such as a foreign substance or an appearance defect on a semiconductor wafer. In addition, the recent foreign-matter inspection equipment has been able to perform appearance defect inspection with the advance of image processing technology, and can be positioned as “scattered light detection type appearance inspection equipment”. Call.

It is assumed that an inspection device group management system 1 including an inspection device A15, an inspection device B25, an inspection device C35, and the like having various detection methods (and thus different models) exists in a semiconductor device manufacturing line. Here, the inspection device A15, the inspection device B25, and the inspection device C35 are referred to as a foreign material inspection device, an appearance defect inspection device, and a simple probe inspection device, respectively. After the inspection, each inspection device (inspection device A15, inspection device B25, inspection device C35) outputs the results for each type, lot, and process (inspection device A product name 11, inspection device A process name 12, inspection device A lot NO1).
3. Inspection device B product name 21, inspection device B process name 22, inspection device B lot NO23, inspection device C product name 31, inspection device C process name 32, inspection device C lot NO33) Transfer to inspection device data collection system 2. I do. The data collection system 2 has a large-scale database (the inspection apparatus A database 14, the inspection apparatus B database 24, and the inspection apparatus C database 34), and stores a process history of an inspection result of the same wafer, a failure occurrence transition of the same process, and the like. It can be used for analysis.

In order to find out a process for generating a large number of defects of a specific type, the data processing unit 4 collects and analyzes data obtained by inspecting the same wafer selected from the specific process using different types of inspection devices of the inspection device group management system 1. By doing so, the correlation degree of the failure distribution map of each inspection device can be calculated, and the inspection device A, C correlation processing result 41 and the inspection device B, C correlation processing result 42 can be obtained. Further, from the correlation degree of the defect distribution map of each inspection device for each of a plurality of types, it is possible to obtain the process condition value of the large number of defective occurrence steps that minimizes the total number of defective occurrences of all types. Then, the data processing unit 4 determines the process condition values of the large number of failure occurrence steps such that the total number of failure occurrences of all types is minimized in the processing step immediately before each inspection apparatus (inspection apparatus A15, inspection apparatus B25, inspection apparatus C35) To instruct.

[0021] The above object is also achieved by a means for inspecting foreign matter,
Means for storing the coordinates of the detected foreign matter in each inspection step, means for performing the preceding step duplicate foreign matter removal processing, means for calculating the number of foreign matter chips in each inspection step, and a defect distribution map of the foreign matter chips and the probe inspection device Means for determining the yield within the number of foreign chips with matching non-defective chips in the module, and means for determining the correlation coefficient of an approximate curve obtained by plotting the relationship between the number of foreign chips and the yield within the number of foreign chips. Means for comparing the correlation coefficient with a preset correlation coefficient management value, means for generating a failure analysis report for each inspection step from the comparison result, and a process apparatus for a process exceeding the correlation coefficient management value Means for sending alarm information to the apparatus, means for importing process condition values of processes exceeding the correlation coefficient management value into the failure analysis database, and a system for managing these inspection apparatus groups. It can be solved by providing a manufacturing method having the beam.

Specifically, by applying the pre-process overlapping foreign matter removal processing to the foreign matter detection result in each inspection step, foreign matter remaining from the step before the inspection target step and newly adhering in the step are removed. Since it is possible to discriminate from the foreign particles, the number of foreign particles and the yield within the number of foreign chips in the inspection target process can be accurately obtained. Therefore, the reliability of the approximation curve indicating the relationship between the number of chips having a foreign substance and the yield within the number of chips having a foreign substance increases, and the determination of the presence / absence of correlation based on the correlation coefficient management value can be performed more accurately. . Therefore, it is possible to accurately and promptly specify a process for generating a large number of foreign substances that reduces the yield and feed back to the process.

In the above-described embodiment, the inspection of foreign substances on a semiconductor wafer has been described as an example. More preferably, in addition to the semiconductor wafer, a wide range of electronic devices such as a printed board, a TFT liquid crystal display, a plasma display, a magnetic disk substrate, etc. It may be applied to parts. Further, the type of inspection is not limited to the foreign substance inspection, and may be applied to an appearance defect inspection.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described in detail below.

First, referring to FIG. 2 to FIG. 17, the correlation calculation processing between the defect distribution maps of the respective inspection apparatuses, the identification of the process of generating a large number of types of defects, and the adjustment of the process conditions of the process of generating a large number of types of defects. Regarding the form, a model will be described using three inspection apparatuses of different models (the first two are foreign substance or appearance defect inspection apparatuses, and the last one is a simple probe inspection apparatus).

As described above, the same wafer is inspected by the inspection device A15 (foreign matter inspection device) and the inspection device B25 (for appearance defect inspection device) having different detection methods, and the same wafer is inspected for defects such as foreign matter and appearance defects. Create a failure distribution map based on the coordinates. Immediately after the end of the inspection by each inspection device, the inspection device C35 (simple probe inspection device) tests the electrical characteristics near the coordinates of the defect such as a foreign substance or an appearance defect.

In this case, a disconnection or a short circuit having the highest capture rate is confirmed by a small tester using a weak current and a weak voltage that do not affect the next processing step. Alternatively, the circuit characteristics may be simulated from a three-dimensional shape measured near the coordinates of a defect such as a foreign substance or an appearance defect, and the quality may be determined as good or defective. When the defect distribution maps of the inspection device A15 and the inspection device C35 are compared with each other, if a chip having a foreign substance or an appearance defect detected by the inspection device A15 is defective by the inspection device C35 (defective mode 1), Chips with foreign matter and appearance defects detected in A15 are inspected by the inspection device C35.
If the test does not cause a failure (failure mode 2), the inspection device A15
In the case where there is a chip (defective mode 3) having a foreign substance, an appearance defect, or the like that could not be detected by the above, it is possible to separately know.

When the results of the matching (overlapping) are displayed in a Venn diagram, they can be classified into two cases as shown in FIGS.

FIG. 5 is a Venn diagram when the inspection results of the inspection device A15 for detecting foreign matter and the inspection device C35 for performing a simple probe inspection are compared.

Here, 10a displayed as a circle is the number of foreign chips detected by the inspection device A15, and 10b is the inspection device C35.
10c is the number of rescue chips detected by the inspection device C35, and 10d is the number of rescue chips detected by the inspection device C35.
Shows the total number of chips tested for both 5 Now, the number of chips in which a foreign substance is detected (defective) by the inspection device A15 is Na (region 10).
a), the number of chips that failed in the inspection device C35 was Nb (area 1
0d-area 10b). The number of chips for which foreign matter has been detected by the inspection device A15 and which has become defective by the inspection device C35 is defined as Nab. The number of defective chips determined to be defective by the inspection device A15 or the inspection device C35 is defined by Equation 1 as Nall.

[0031]

(Equation 1)

The presence or absence of the degree of correlation between the two models is calculated by Equation 2.

[0033]

(Equation 2)

R1 indicates the number of defects detected by the inspection apparatus C35 based on the number of foreign substances detected by the inspection apparatus A15 (Equation 2).
A threshold value T1 (for example, 0.9) is set for R1. If the threshold value T1 is exceeded, the inspection devices A15 and C35 indicate that the defective chip has become defective due to foreign matter.

FIG. 6 is a Venn diagram between an inspection device B25 for detecting an appearance defect and an inspection device C35 for performing a simple probe inspection.

Here, 11a displayed as a circle is the number of appearance defect chips detected by the inspection device B25, 11b is the number of non-defective chips detected by the inspection device C35, and 11c is the rescue non-defective chips detected by the inspection device C35. The number 11d indicates the total number of chips inspected by both the inspection apparatus B25 and the inspection apparatus C35.

Now, the number of chips whose appearance defect is detected (defective) by the inspection apparatus B25 is defined as Ma (area 11a), and the number of chips failed by the inspection apparatus C35 is defined as Mb (area 11d-area 11b). The number of chips that have been detected by the inspection device B25 and have become defective by the inspection device C35 is defined as Mab. The number of defective chips determined to be defective by the inspection device B25 or the inspection device C35 is defined by Equation 3 as Mall.

[0038]

(Equation 3)

The presence or absence of the degree of correlation between the two models is calculated by Equation 4.

[0040]

(Equation 4)

R2 indicates the number of defects detected by the inspection apparatus C35 based on the number of appearance defects detected by the inspection apparatus B25 (Equation 2). A threshold value T2 (for example, 0.9) is set for R2. If the threshold value T2 is exceeded, it indicates that the inspection device C35 has failed due to the appearance defect of the inspection device B25.

FIGS. 7 to 12 show a method of judging the degree of correlation between the inspection devices obtained from different viewpoints. This determination method is given by Equation 1.
Can be used in combination with the correlation degree of Equation (4) or used alone.

FIGS. 7 to 9 are diagrams showing the relationship between the number of defective chips detected by the inspection device A15 and the number of non-defective chips detected by the inspection device C35. The solid line in the figure shows the correlation curve of chip data with foreign matter, and the broken line shows the correlation curve of chip data without foreign matter. The threshold value of the correlation coefficient of the curves shown in FIGS. 7 to 9 is T3, and the threshold value of the slope of the curves is T4 (negative).

In FIG. 7, the number of non-defective chips detected by the inspection device C35 is constant regardless of the number of defective chips detected by the inspection device A15. At this time, it is assumed that the correlation coefficient and the slope of the curve are smaller than threshold values T3 and T4, respectively. At this time, it is determined that there is no correlation.

FIG. 8 shows a case where the number of defective chips detected by the inspection device C35 decreases as the number of defective chips detected by the inspection device A15 increases. In this case, the absolute value of the correlation coefficient and the absolute value of the slope of the curve are larger than the threshold values T3 and T4, respectively, and the result of the correlation degree calculation processing is that "there is a correlation and there are many probe inspection failures due to foreign matter in this step." Will be issued. In this case, an instruction to readjust the process condition value of the inspection apparatus A15 is issued.

FIG. 9 shows a case where the number of non-defective chips detected by the inspection device C35 increases as the number of foreign chips detected by the inspection device A15 increases. At this time, the correlation coefficient and the slope of the curve are larger than the thresholds T3 and T4, respectively, but the slope of the curve is opposite in sign to the threshold T4. In the correlation degree calculation processing, the result is "No correlation. In this step, there are many probe inspection failures other than those caused by foreign substances."

FIG. 10 is a diagram showing the spread of each data on the curve of FIG.

Let K1 be the correlation coefficient of the chip data with foreign matter, and let e1 be the slope of the correlation curve. The correlation coefficient of the chip data without foreign matter is K2, and the slope of the correlation curve is e2. Here, the threshold value for judging the presence or absence of the correlation between the inspection device A15 and the inspection device C35 based on the magnitude of the correlation coefficient is set to K0 (example 0.8).

The correlation coefficient K1 of the chip with foreign matter is equal to the threshold value K0
If the number exceeds the threshold, there is a correlation between the inspection apparatus A15 and the inspection apparatus C35, and it is determined that the probe inspection failure of the inspection apparatus C35 is caused by the foreign matter detected by the inspection apparatus A15.
In this case, an instruction to readjust the process condition value of the inspection apparatus A15 is issued. If the correlation coefficient K2 of the chip-free chip data exceeds the threshold value K0, the chip without chip also has another defect generation factor due to the foreign matter. You will be instructed to readjust.

FIGS. 11 to 14 show the relationship between the inspection device B25 for inspecting appearance defects and the inspection device C35 for probe inspection, and the determination method is the same as in FIGS. 7 to 10.

FIGS. 11 to 13 are diagrams showing the relationship between the number of appearance defective chips detected by the inspection device B25 and the number of non-defective chips detected by the inspection device C35. The solid line in the drawing indicates the correlation curve of the chip data having the appearance defect, and the broken line indicates the correlation curve of the chip data having no foreign matter. The threshold value of the correlation coefficient of the curves shown in FIGS. 11 to 13 is T5, and the threshold value of the slope of the curves is T6 (negative).

In FIG. 11, the number of non-defective chips detected by the inspection device C35 is constant regardless of the number of appearance defect chips detected by the inspection device B25. It is assumed that the correlation coefficient and the slope of the curve at this time are smaller than threshold values T5 and T6, respectively. At this time, it is determined that there is no correlation.

FIG. 12 shows a case where the number of non-defective chips detected by the inspection device C35 decreases as the number of defective chips detected by the inspection device B25 increases. In this case, the absolute value of the correlation coefficient and the absolute value of the slope of the curve are larger than the threshold values T5 and T6, respectively. In the correlation degree calculation processing, "there is a correlation, and there are many probe inspection failures due to appearance defects in this step." You will get results. In this case, an instruction to readjust the process condition value of the inspection device B25 is issued.

FIG. 13 shows a case where the number of non-defective chips detected by the inspection device C35 increases as the number of appearance defective chips detected by the inspection device B25 increases. At this time, the correlation coefficient and the slope of the curve are larger than the thresholds T5 and T6, respectively, but the slope of the curve is opposite in sign to the threshold T6. In the correlation degree calculation process, the result is "No correlation. In this step, there are many probe inspection failures other than those caused by appearance defects."

FIG. 14 is a diagram showing the spread of each data on the curve in FIG.

Let K3 be the correlation coefficient of the chip data with foreign matter, and let e3 be the slope of the correlation curve. The correlation coefficient of the chip data without foreign matter is K4, and the slope of the correlation curve is e4. Here, the threshold value for judging the presence or absence of the correlation between the inspection device B25 and the inspection device C35 based on the magnitude of the correlation coefficient is set to K0 '(0.8).

The correlation coefficient K1 of the chip with foreign matter is equal to the threshold value K
If it exceeds 0 ', there is a correlation between the inspection apparatus B25 and the inspection apparatus C35, and it is determined that the probe defect of the inspection apparatus C35 is caused by the appearance defect detected by the inspection apparatus B25. In this case, an instruction to readjust the process condition value of the inspection device B25 is issued. If the correlation coefficient K2 of the chip with no appearance defect exceeds the threshold value K0 ', the chip with no appearance defect also has another defect generation factor due to foreign matter. The instruction to readjust the condition value will be given.

In the description of FIG. 7 to FIG. 14, the chip which is the judgment unit of the probe test of the test apparatus C35 is used as the constituent unit of the correlation curve data, but the bit number unit used in the fail bit map is used. , Foreign matter unit,
A unit of the number of appearance defects, a unit of a wafer in which all chips in the same wafer are totalized, or a unit of a total of all wafers in the same lot may be used.

FIG. 15 shows an inspection apparatus A15 or an inspection apparatus B25.
FIG. 5 is a diagram of a small tester for checking electrical characteristics (disconnection or short circuit) of defective coordinates immediately after the inspection.

The data processing unit 4 is an inspection device A database
14 or a defect detection position such as a foreign matter or an appearance defect from the inspection device B database 24 (inspection device A, B defective portion 7
The coordinate data of 3) is sent to the inspection device C35. Inspection device C35
The small testers 351 and 352 are brought into contact with the in-chip circuit wiring 72 including the defective detection part based on the obtained coordinate data, and an inspection for disconnection and short-circuit is performed. The inspection result is stored in the inspection device C database, and is used for calculating the degree of correlation with the inspection result of the inspection device A15 or the inspection device B25.

FIG. 16 shows an inspection apparatus A15 or an inspection apparatus B25.
FIG. 6 is a schematic diagram in a case where a three-dimensional shape of a circuit near defective coordinates is measured immediately after the inspection and a circuit characteristic is simulated from the measured shape.

As in FIG. 15, the data processing unit 4 uses the inspection device A database 14 or the inspection device B database 24 to detect a defect (such as a foreign object or an external appearance defect) such as a defect (inspection device A,
The coordinate data of the B defect location 73) is sent to the inspection device C35. The inspection device C35 observes the CCD devices 353 and 354 from different directions based on the obtained coordinate data, and generates a three-dimensional three-dimensional shape of the circuit wiring in the chip including the defective portions of the inspection devices A and B. Next, the probe inspection results (electrical characteristics) after the completion of all the processing steps are compared with the simulation database 355 of the electric characteristics obtained from the many measured three-dimensional shapes and the three-dimensional shape generated this time. Estimate whether a disconnection or short circuit has occurred. The estimation result is taken into the inspection apparatus C database, and the correlation degree is calculated.

FIG. 17 summarizes the concept of the inspection flow according to the present invention.

First, the type name, process name, and lot number of a wafer to be monitored by each inspection device are initialized. After the wafer is loaded and the processing step N81 is completed, foreign matter is detected by the inspection device A15, and immediately thereafter, a simple probe inspection is performed by the inspection device C35.
Next, after completion of the processing step M82, the appearance defect is detected by the inspection device B25, and immediately after that, a simple probe inspection is performed by the inspection device C35. According to the progress of the processing process, the correlation degree calculation processing between the respective inspection devices is automatically performed at regular intervals, and when each exceeds the set threshold value, the process condition value of the process is readjusted, High wafer yield can be maintained.

The first embodiment of the present invention has been described by taking as an example the inspection of a foreign substance or an appearance defect on a semiconductor wafer. However, the inspection target is a bit-by-bit inspection (failure) in each chip of the wafer. Bit inspection) can be considered in the same way, and a failure bit inspection device and an inspection device A1
5, correlation determination with the inspection device B25 and the inspection device C35 may be added. In this case, since the degree of correlation is compared for each bit, the data amount increases and the reliability increases. In addition, the unit of correlation degree comparison is bit unit,
In addition to the chip unit, the inspection may be performed on the appearance defect occurrence location unit, the foreign matter occurrence location unit, the wafer unit, and the lot unit.

In addition, the present invention can be applied to a high yield production of a wide range of electronic components such as a printed circuit board, a TFT liquid crystal display device, a plasma display type display device, and a magnetic disk substrate in addition to a semiconductor wafer.

Next, a second embodiment of the present invention will be described.
This will be described in detail below.

First, referring to FIG. 18 to FIG. 23, the process of removing the duplicate foreign matter in the preceding process is performed from the foreign matter detected by the inspection apparatus A15 in FIG. 1, and the relationship between the number of foreign matter chips on each semiconductor wafer and the yield in the foreign matter chips. An embodiment will be described in which an approximation curve indicating the following is obtained, and when the correlation coefficient of the approximation curve exceeds a predetermined management value, alarm information is transmitted to the corresponding process apparatus.

FIG. 18 is a diagram showing an example in which a foreign matter detected by the inspection apparatus A15 shown in FIG. 1 is subjected to a pre-process duplicate foreign matter elimination process, and an approximate curve showing the relationship between the number of foreign chips and the yield in foreign chips of each semiconductor wafer is obtained. The process of sending alarm information to a corresponding process device when the correlation coefficient of the approximate curve exceeds a predetermined management value is shown in the form of a flowchart.

In step 51, N = 1 is set in preparation for performing the processing in the first inspection step. Next, in step 52, since N = 1, the entire surface of the semiconductor wafer in the first inspection step is inspected by the inspection apparatus A15 in FIG. 1, and a foreign matter map shown in FIG. 19 is created. In step 53, it is determined whether the current inspection step is the first inspection step or the second or later inspection step. If the current inspection step is the first inspection step, there is no previous inspection step, so that the processing skips step 54 (previous step duplicate foreign matter deletion processing). Next, in step 55, it is confirmed whether there is a semiconductor wafer yet to be inspected in the same lot. If there is an untested semiconductor wafer in the same lot, the process returns to step 52.
If all have been inspected, the process proceeds to step 56. In step 56, it is confirmed whether or not the current inspection step is the final inspection step. If it is not the final inspection process, the process proceeds to step 57, where the process proceeds to the next inspection process after the current inspection process. In this case, since N = 1, the next inspection process is the second (N =
2). Upon completion of the process in the step 57, the process returns to the step 52, and a foreign matter map of the semiconductor wafer in the second inspection process is created. In this manner, the processing from step 52 to step 56 is repeated until the processing of all the semiconductor wafers in the final inspection step is completed.

If it is determined in step 56 that N is the final inspection step, the process proceeds to step 58. In step 58, step 59
In order to prepare the total of the number of foreign chips and the yield in foreign chips for each semiconductor wafer, N = 1 is set.

In step 59, the number of foreign particles for each chip of the semiconductor wafer in the first inspection process is calculated. Next, the number of chips with the number of foreign substances of 1 or more (the number of chips with foreign substances) is totaled. The number of chips with foreign matter is totaled for each of the number of non-defective chips in the probe test and the number of defective chips in the probe test with reference to the inspection device C database 34 (probe inspection device database) in FIG.
By dividing the number of non-defective chips in the probe test by the sum of the number of non-defective chips in the probe test and the number of defective chips in the probe test, it is possible to obtain the yield in the foreign-material-containing chip of the semiconductor wafer which is currently tabulated. Then go to step 60,
Check whether there are uncounted semiconductor wafers in the same lot. Step if there are uncounted semiconductor wafers
Returning to step 59, the same processing is repeated until there is no uncounted wafer.

When the processing for one lot is completed, the process proceeds to step 61. In step 61, the relationship between the number of chips with foreign matter and the yield in the chip with foreign matter of each semiconductor wafer in the first inspection process that is currently being processed is plotted, and the correlation coefficient of the obtained approximate curve is obtained.

In step 62, it is confirmed whether or not the correlation coefficient of the obtained approximate curve exceeds a preset management value. If it exceeds the control value, the process proceeds to step 63, in which notification information indicating that there is a correlation with respect to the relationship between the number of foreign chips in the semiconductor wafer and the yield in the foreign chip is generated. The notification information with correlation in step 63 is sent to step 64 as it is, and a failure analysis report for each inspection process including the notification information with correlation is generated. If the control value does not exceed the control value in step 62, the flow directly proceeds to step 64 to generate a failure analysis report for each inspection process only for the number of chips with foreign matter and the yield data in the chip with foreign matter.

After generating a failure analysis report for the first inspection process in step 64, the flow advances to step 65 to check whether N is the final inspection process. Since the current inspection process is the first, the process proceeds to step 66, and returns to step 59 with N = 2.

As described above, steps 59 to 65 are performed.
Are performed up to the final inspection step, and the routine proceeds to step 67. In step 67, it is confirmed from the failure analysis report for each inspection process whether or not there is a process exceeding the correlation coefficient management value in all inspection processes. If there is a process exceeding the control value, the process proceeds to step 68, where alarm information is sent to the process device of that process. Next, the process proceeds to step 69, where the process condition value of the process is taken into the failure analysis database.
Next, the routine proceeds to step 91, where a series of processing is terminated. By continuing this processing, it is possible to grasp the tendency of the process condition value in the process of generating a large number of foreign substances that reduces the yield. If there is no process exceeding the correlation coefficient management value in all the inspection processes in step 67, the process jumps to step 91 to end a series of processes.

As described above, by applying the pre-process overlapping foreign matter removal processing of step 54 to the foreign matter detection result in each inspection step, foreign matter remaining from the step before the inspection target step and new foreign matter in that step are obtained. Since it is possible to separate the foreign matter from the foreign matter attached to the semiconductor chip, the number of foreign matter chips and the yield within the foreign matter chip number in the inspection target process can be accurately obtained.
Therefore, the reliability of the approximate curve indicating the relationship between the number of the foreign particle chips and the yield within the foreign particle chip number increases,
The determination of the presence / absence of correlation based on the correlation coefficient management value can be performed more accurately. Therefore, the process of generating a large number of foreign substances that reduces the yield can be accurately and quickly performed, and a high yield of the semiconductor wafer can be maintained.

FIG. 19 shows a map of a foreign substance detected in the Nth inspection step of the inspection apparatus A. Foreign substances 201 to 2 detected on the semiconductor wafer 200 in the Nth inspection process of the inspection apparatus A
10 have been detected.

FIG. 20 shows a map of the foreign matter detected in the (N-1) th inspection step of the inspection apparatus A. Semiconductor wafer 200
Above, the foreign substances 301 to 309 detected in the (N-1) th inspection step of the inspection apparatus A are detected.

FIG. 21 shows a map of the foreign substance detected in the N-th inspection step of the inspection apparatus A, in which the coordinates of the foreign substance detected in the preceding step are compared with those of the foreign substance. The foreign substances 204, 205, 209 detected in the Nth inspection step where the coordinates between the detected foreign substances in the inspection step are within the positioning error of the inspection apparatus A15 and the foreign substances 201, 202, 203, 206, 207, 208, newly detected in the Nth inspection step of the inspection apparatus A
210 is shown.

FIG. 22 shows the Nth and Nth maps from the map of FIG.
The coordinates between the foreign matter detected in the first inspection process are the inspection device A15
Foreign matter 201, 202, 203, 206, 207, 208, foreign matter 204, 205, 209 detected in the Nth inspection step within the positioning error is removed and newly detected in the Nth inspection step of the inspection apparatus A.
210 is shown.

FIG. 23 is a flowchart showing a method of removing foreign matter from the preceding process in step 54 of FIG. In step 542, the N generated in step 52 in FIG.
Using the data of the foreign matter map of the Nth inspection step as it is, a foreign matter coordinate database of the semiconductor wafer of the Nth inspection step is created. In step 543, a foreign substance coordinate database of the semiconductor wafer in the (N-1) th inspection step is similarly created using the foreign substance map data of the same semiconductor wafer in the (N-1) th inspection step in the immediately preceding step.

Next, at step 544, an initial value of the number of repetitions (ie, an initial value of the number of repetitions (for comparing the first particle coordinates of the semiconductor wafer in the Nth inspection step with the first particle coordinates of the same semiconductor wafer in the (N-1) th inspection step) is compared. i = 1, j = 1) are set.

Next, at step 545, the i-th foreign matter coordinates (Ai, Bi) of the semiconductor wafer in the N-th inspection step and N-
It is confirmed whether or not the distance from the j-th foreign matter coordinate (Cj, Dj) of the same semiconductor wafer in the first inspection step is within the positioning error of the inspection apparatus A15.

Assuming that the positioning error is δ, (Ai, B
The expression for determining whether the distance between i) and (Cj, Dj) is within δ is defined by Equation 5.

[0086]

(Equation 5)

When the distance between (Ai, Bi) and (Cj, Dj) is within δ, the process proceeds to step 546, where the detection coordinates (Ai, Bi) are obtained from the database of the semiconductor wafer in the Nth inspection step.
The foreign matter in Bi) is deleted, and the flow advances to step 547. (Ai,
When the distance between (Bi) and (Cj, Dj) is not within δ, (Ai, Bi) and (Cj, Dj) are determined to be different foreign substances, and the process proceeds to step 547.

In step 547, the number of repetitions j is N-1.
It is checked whether the number is equal to the number q of detected foreign substances of the same semiconductor wafer in the second inspection step. If not, step 54
Proceeding to 7a, increase the number of repetitions j by 1 and return to step 545. In this way, the processes of steps 545 and 546 are repeated until the number of repetitions j = q.

If j = q, the flow advances to step 548 to check whether or not the number of repetitions i is equal to the number of detected foreign substances p in the Nth inspection step. Step if not equal
Proceeding to 548a, the number of repetitions i is increased by 1 and the process returns to step 545. In this way, the processing of steps 545 and 546 is repeated until the number of repetitions i = p. If i = p, the process proceeds to step 549, and the previous-process duplicate foreign matter removal processing ends.

In the example shown in FIG. 23, the processing for removing only the foreign substance detected redundantly in the immediately preceding inspection step has been described.
N-1 from the first foreign matter detected in the inspection process
The processing may be a processing for removing all the foreign substances detected in duplicate in the inspection steps up to the first.

In FIG. 23, only one step (steps from the first inspection step to N
When the number of combinations is N-1 until the first inspection step), when only two steps are used (first inspection step to N-
The combination up to the first inspection process is (N-1). (N-
2) / 2) When only three processes are used (from the first inspection process to the (N-1) th inspection process, the combination is (N-1).
(N−2) · (N−3) / (3 · 2),..., N−2 processes only (N-1 combinations from the first inspection process to the (N−1) th inspection process) ), And only N-1 steps (one combination from the first inspection step to the N-1st inspection step, one combination) is performed, and the positioning error of the inspection apparatus A in each case is determined. The number of duplicate foreign substances within the range is obtained, and the inspection process in which the number of duplicate foreign substances exceeds the preset foreign substance number management value n is automatically added to the inspection process failure analysis report of step 64 in FIG. Good. In this case, since it is possible to know in which inspection step the residual foreign matter generated in a specific process can be seen, feedback is applied mainly to the process in which the residual foreign material appears.

The second embodiment of the present invention has been described above with reference to FIGS. 18 to 23 by taking as an example the inspection of a foreign substance on a semiconductor wafer. Is also good. In addition, the present invention can be applied to a high yield production of a wide range of electronic components such as a printed circuit board, a TFT liquid crystal display device, a plasma display type display device, and a magnetic disk substrate in addition to a semiconductor wafer.

[0093]

As described above, according to the present invention, in the manufacture of a semiconductor wafer, a printed circuit board, a TFT liquid crystal display device, a plasma display type display device, and a magnetic disk substrate, the process condition values can always be kept optimal. It can greatly contribute to high yield manufacturing.

Semiconductor wafers, printed circuit boards, TFTs
In the manufacture of liquid crystal display devices, plasma display devices, and magnetic disk substrates, pre-process duplicate foreign matter removal processing is applied to the foreign matter detection results in each inspection process, thereby remaining from processes before the inspection target process. Since it is possible to separate the foreign matter that is present and the foreign matter newly attached in the process, it is possible to accurately obtain the number of foreign matter chips and the yield within the number of foreign matter chips in the inspection target process. Therefore, the reliability of the approximation curve indicating the relationship between the number of chips having a foreign substance and the yield within the number of chips having a foreign substance increases, and the determination of the presence / absence of correlation based on the correlation coefficient management value can be performed more accurately. . Therefore, it is possible to accurately and promptly identify the process of generating a large number of foreign substances which lowers the yield and to feed back to the process.
FT liquid crystal display, plasma display type display,
High yield can be maintained in the manufacture of magnetic disk substrates.

Further, by using the failure analysis database, it is possible to grasp the tendency of the process condition value in the process of generating a large number of foreign substances that reduces the yield.

[Brief description of the drawings]

FIG. 1 is a processing functional block diagram showing a first embodiment of the present invention.

FIG. 2 is a view showing a foreign matter generation location of the inspection apparatus A;

FIG. 3 is a diagram showing locations where an appearance defect occurs in the inspection apparatus B;

FIG. 4 is a diagram showing a failure point of the probe inspection of the inspection apparatus C;

FIG. 5 is a Venn diagram of the inspection device A and the inspection device C.

FIG. 6 is a Venn diagram of the inspection device B and the inspection device C.

FIG. 7 is a diagram showing a correlation curve between an inspection device A and an inspection device C.

FIG. 8 is a diagram showing a correlation curve between the inspection device A and the inspection device C.

FIG. 9 is a diagram showing a correlation curve between the inspection device A and the inspection device C.

FIG. 10 is a diagram showing a correlation curve between an inspection device A and an inspection device C.

FIG. 11 is a diagram showing a correlation curve between the inspection device B and the inspection device C.

FIG. 12 is a diagram showing a correlation curve between an inspection device B and an inspection device C.

FIG. 13 is a diagram showing a correlation curve between the inspection device B and the inspection device C.

FIG. 14 is a diagram showing a correlation curve between the inspection device B and the inspection device C.

FIG. 15 is a diagram showing a first example of a simple probe test.

FIG. 16 is a diagram showing a second embodiment of the simple probe test.

FIG. 17 is a diagram showing a concept regarding a flow of inspection according to the present invention.

FIG. 18 is a processing function block diagram showing a second embodiment of the present invention.

FIG. 19 is a map of a foreign substance detected in an N-th inspection step of the inspection apparatus A.

FIG. 20 is a map of a foreign substance detected in the (N-1) th inspection step of the inspection apparatus A.

FIG. 21 is a map of a foreign substance detected in an N-th inspection step of the inspection apparatus A.

FIG. 22 is a foreign substance map newly detected in the N-th inspection step of the inspection apparatus A.

FIG. 23 is a processing functional block diagram showing a pre-process duplicate foreign matter removal process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Inspection apparatus group management system, 11 ... Inspection apparatus A kind name, 12 ... Inspection apparatus A process name, 13 ... Inspection apparatus A lot number, 14 ... Inspection apparatus A database, 15 ... Inspection apparatus A, 21 ... Inspection apparatus C Product name, 22: Inspection device C process name, 23: Inspection device C lot No., 24: Inspection device C database, 25: Inspection device B, 31: Inspection device B product name, 32: Inspection device B process name, 33 ... Inspection device B lot NO, 34: Inspection device B database, 35: Inspection device C, 4: Data processing unit, 41: Inspection device A, C correlation processing result, 42: Inspection device B, C correlation processing result, 10a: Foreign matter Number of existing chips, 10b: Number of good chips for probe inspection,
10c: Number of non-defective chips for probe inspection, 10d: Total number of chips, 11a: Number of externally defective chips, 11b: Number of non-defective chips for probe inspection, 11d: Total number of chips, 7: Semiconductor wafer, 71: Chip for foreign matter or external defects 351, 3
52: Small tester, 353, 354: CCD camera,
Reference numeral 355: simulation database, 72: circuit wiring in a chip, 73: inspection device A, B defective part, 81: processing step N, processing step M, 200: semiconductor wafer, 20
1,202,203,204,205,206,20
7, 208, 209, 210... Foreign substances detected in the Nth inspection step, 301, 302, 303, 304, 305, 30
6, 307, 308, 309... Foreign substances detected in the (N-1) th inspection step.

Continued on the front page (72) Minoru Noguchi Minoru Noguchi 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.

Claims (18)

[Claims] In a semiconductor device manufacturing line including a plurality of processing steps, a semiconductor device of a specific type is constantly extracted or 100% inspected by using a plurality of inspection apparatuses having different detection methods from a semiconductor device having undergone a predetermined processing step. Immediately after that, a partial area (10 chips or more) on the semiconductor device having many defects (adhesion foreign matters, appearance defects, bit defects, etc.) detected by the plurality of inspection devices affects subsequent processing steps. A simple probe test for detecting disconnection and short-circuit by applying no minute current and voltage, and comparing the correlation between the test results detected by the plurality of test devices and the simple probe test results to obtain a final probe test A semiconductor device manufacturing method, wherein a processing step in which a large number of fatal failures are likely to occur is identified at an early stage, and the process conditions of the step are readjusted. 2. The semiconductor device manufacturing method according to claim 1, wherein the unit of the correlation curve data configuration is the same as the number of bits, the number of foreign particles, the number of external defects, and the number of chips in the same wafer of the semiconductor device. A method of manufacturing a semiconductor device, wherein the method is a wafer unit. 3. The semiconductor device according to claim 1, wherein a plurality of types of semiconductor devices are constantly sampled or 100% inspected, and process condition values are readjusted for each type. Production method. 4. The method according to claim 1, wherein a plurality of types of semiconductor devices are constantly sampled or 100% inspected, and the process condition values are readjusted so that the total failure rate of all types is minimized. The method for manufacturing a semiconductor device according to any one of the above. 5. The method for manufacturing a semiconductor device according to claim 3, wherein after a simple probe test, a defect rate is tabulated for each defect class, and the test result detected by said plurality of test devices and the simplified test result. By comparing the degree of correlation with the failure rate for each failure classification of the probe inspection results, to identify the type of failure that is fatal failure based on foreign matter and appearance defects, based on the identified type of failure process condition value A method for manufacturing a semiconductor device, wherein readjustment is performed. 6. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 1. 7. In a semiconductor device manufacturing line comprising a plurality of processing steps, a semiconductor device of a specific type is constantly extracted or 100% inspected by using a plurality of inspection apparatuses having different detection methods from a semiconductor device having undergone a predetermined processing step. Immediately after that, in a non-contact three-dimensional circuit pattern of a partial area (10 chips or more) on the semiconductor device having many defects (attached foreign matter, appearance defect, bit defect, etc.) detected by the plurality of inspection devices. A measurement is performed to simulate the operation characteristics of the circuit (pseudo-probe inspection), and a comparison between the inspection results detected by the plurality of inspection devices and the simulation result (pseudo-probe inspection result) is performed. A semiconductor process characterized in that a processing step in which many fatal defects are likely to occur is identified early, and the process conditions of the step are readjusted. Device manufacturing method. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the unit of the correlation curve data structure is the same as the number of bits, the number of foreign particles, the number of external defects, and the number of chips in the same wafer of the semiconductor device. A method of manufacturing a semiconductor device, wherein the method is a wafer unit. 9. The semiconductor device according to claim 7, wherein a plurality of types of semiconductor devices are constantly extracted or 100% inspected, and the process condition value is readjusted for each type. Production method. 10. A semiconductor device of a plurality of types is constantly extracted or 100% inspected, and process condition values are readjusted so as to minimize the total failure rate of all types of semiconductor devices. The method for manufacturing a semiconductor device according to any one of the above. 11. The method of manufacturing a semiconductor device according to claim 7, wherein after performing a non-contact three-dimensional measurement of the circuit pattern to simulate the operation characteristics of the circuit (pseudo-probe inspection), the expected number of defects is determined for each defect. The defect rate for each category is tabulated, and the degree of correlation between the inspection results detected by the plurality of inspection devices and the defect rate for each failure category of the pseudo probe inspection result is compared. A method of manufacturing a semiconductor device, comprising: identifying a type of a defect to be defective; and re-adjusting a process condition value based on the identified type of the defect. 12. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 7. 13. In a semiconductor device manufacturing line including a plurality of processing steps, a semiconductor device of a specific type is constantly extracted or 100% inspected by using a plurality of inspection apparatuses having different detection methods from a semiconductor device having undergone a predetermined processing step. In the semiconductor device manufacturing method, the coordinates of the detected foreign matter or detected appearance defect in the processing step currently being inspected are compared with the coordinates of the detected foreign matter or detected appearance defect in the immediately preceding processing step, and the positioning accuracy of the inspection apparatus is determined. Within the error range, the number of foreign substances or appearance defects detected in both processes in duplicate is removed from the number of foreign substances or appearance defects detected in the processing step currently being inspected, and the current inspection is performed. The number of foreign substances or the number of appearance defects newly detected in the processing step in which the number of newly generated foreign substances or the number of newly generated appearance defects are compared with the final probe inspection result. Te, final fatal defect in the probe test to identify likely treatment step of generating many early, the semiconductor device manufacturing method characterized by performing the readjustment process conditions of said process. 14. The semiconductor device manufacturing method according to claim 13, wherein the processing step of comparing with the coordinates of the detected foreign matter or the detected appearance defect of the processing step currently being inspected is the same as that of the current inspection step. A method of manufacturing a semiconductor device, comprising all steps up to the previous step. 15. The method of manufacturing a semiconductor device according to claim 13, wherein the number of newly generated foreign particles or the number of newly generated appearance defects is totaled for each chip to obtain the number of foreign particles. Semiconductor device manufacturing method. 16. A method of manufacturing a semiconductor device according to claim 13, wherein only one processing step (first inspection step to N- When the number of combinations is N-1 for the first inspection step, the combination is only for two steps (from the first inspection step to the (N-1) th inspection step, the combination is (N-1). (N -2) / 2) When only three processes are performed (the combination from the first inspection process to the (N-1) th inspection process is (N-1). (N-2). (N-3) / ( 3.
2)),..., N-2 steps only (N-1 combinations from the first inspection step to the N-1st inspection step), and N-1 steps only (first step) Inspection process ~
All combinations (one combination up to the (N-1) th inspection step) are performed, and the number of overlapping foreign substances within the range of the positioning error of the inspection apparatus in each case is obtained, and the preset foreign substance number management is performed. A method for manufacturing a semiconductor device, comprising: automatically identifying an inspection step in which the number of overlapping foreign substances exceeding a value is found, and re-adjusting process conditions of the step. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the number of newly generated foreign substances or the number of newly generated appearance defects is totaled for each chip to obtain the number of chips with foreign substances. 18. A semiconductor device manufactured by the method according to claim 13.