JPS55139695A - Testing method for memory unit - Google Patents

Testing method for memory unit

Info

Publication number
JPS55139695A
JPS55139695A JP4399979A JP4399979A JPS55139695A JP S55139695 A JPS55139695 A JP S55139695A JP 4399979 A JP4399979 A JP 4399979A JP 4399979 A JP4399979 A JP 4399979A JP S55139695 A JPS55139695 A JP S55139695A
Authority
JP
Japan
Prior art keywords
information
read
write
registers
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4399979A
Other languages
Japanese (ja)
Other versions
JPS6230463B2 (en
Inventor
Hidehiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4399979A priority Critical patent/JPS55139695A/en
Publication of JPS55139695A publication Critical patent/JPS55139695A/en
Publication of JPS6230463B2 publication Critical patent/JPS6230463B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To take a high-speed test by making a comparison between the write information and read information of registers for interleaving write information according to the assignment of a test condition attaching signal, in a memory unit performing interleaving operation.
CONSTITUTION: In not less than three memory element groups 11, 21... for interleaving, information is written via not less than three write information registers 10, 20... stored with one of not less than three kinds of information. Through a controller applied with read/write, address and test condition attaching signals 51W54 phaced in start and read states, comparing circuit 15 makes a comparison between a write signal read out from registers 10, 20... and made by selector circuit 14 to agree with the test condition assignment, and read information from elements 11, 21... written in read information registers 22... to write and read the information at respective addresses of the memory elements, and the memory unit is tested rapidly without three kinds of operation such as further comparison.
COPYRIGHT: (C)1980,JPO&Japio
JP4399979A 1979-04-11 1979-04-11 Testing method for memory unit Granted JPS55139695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4399979A JPS55139695A (en) 1979-04-11 1979-04-11 Testing method for memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4399979A JPS55139695A (en) 1979-04-11 1979-04-11 Testing method for memory unit

Publications (2)

Publication Number Publication Date
JPS55139695A true JPS55139695A (en) 1980-10-31
JPS6230463B2 JPS6230463B2 (en) 1987-07-02

Family

ID=12679403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4399979A Granted JPS55139695A (en) 1979-04-11 1979-04-11 Testing method for memory unit

Country Status (1)

Country Link
JP (1) JPS55139695A (en)

Also Published As

Publication number Publication date
JPS6230463B2 (en) 1987-07-02

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