JPS5637894A - High-speed memory testing method - Google Patents

High-speed memory testing method

Info

Publication number
JPS5637894A
JPS5637894A JP11076779A JP11076779A JPS5637894A JP S5637894 A JPS5637894 A JP S5637894A JP 11076779 A JP11076779 A JP 11076779A JP 11076779 A JP11076779 A JP 11076779A JP S5637894 A JPS5637894 A JP S5637894A
Authority
JP
Japan
Prior art keywords
address
tester
test
speed
testing method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11076779A
Other languages
Japanese (ja)
Inventor
Hiroharu Hiratsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11076779A priority Critical patent/JPS5637894A/en
Publication of JPS5637894A publication Critical patent/JPS5637894A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable a tester of a low-speed test cycle to test a high-speed-cycle memory to be tested, by using an address from the tester and that from an artificial address counter.
CONSTITUTION: The 1st address from the tester and the 2nd address from artificial address counter 11 are stored 12 and 15 and through the time-division operation of multiplexer 17, they are supplied alternately to memory 18 to be tested at high-speed cycles. Then, test data are written at the 1st address from the tester first and read out from the 2nd address; and they are read out alternately by using the 1st and 2nd address; thereby finishing a single test. Next, read data obtained by using the 2nd address are sequentially compared 26 and 27 to make sure 28 of their identity and at the same time, write data by the 1st address and following read data are checked in terms of characteristics.
COPYRIGHT: (C)1981,JPO&Japio
JP11076779A 1979-08-30 1979-08-30 High-speed memory testing method Pending JPS5637894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11076779A JPS5637894A (en) 1979-08-30 1979-08-30 High-speed memory testing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11076779A JPS5637894A (en) 1979-08-30 1979-08-30 High-speed memory testing method

Publications (1)

Publication Number Publication Date
JPS5637894A true JPS5637894A (en) 1981-04-11

Family

ID=14544055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11076779A Pending JPS5637894A (en) 1979-08-30 1979-08-30 High-speed memory testing method

Country Status (1)

Country Link
JP (1) JPS5637894A (en)

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