JPS5673354A - Testing device for ic - Google Patents

Testing device for ic

Info

Publication number
JPS5673354A
JPS5673354A JP15089479A JP15089479A JPS5673354A JP S5673354 A JPS5673354 A JP S5673354A JP 15089479 A JP15089479 A JP 15089479A JP 15089479 A JP15089479 A JP 15089479A JP S5673354 A JPS5673354 A JP S5673354A
Authority
JP
Japan
Prior art keywords
blocks
test
separated
expected value
defect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15089479A
Other languages
Japanese (ja)
Inventor
Kenji Kimura
Koji Ishikawa
Naoaki Narumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Advantest Corp
Nippon Telegraph and Telephone Corp
Takeda Riken Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp, Nippon Telegraph and Telephone Corp, Takeda Riken Industries Co Ltd filed Critical Advantest Corp
Priority to JP15089479A priority Critical patent/JPS5673354A/en
Publication of JPS5673354A publication Critical patent/JPS5673354A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To enable to store various kinds of data by each different timing and to reduce a test time by a method wherein a sequence memory is separated into a plural number of blocks and a write operation is controlled according to each block.
CONSTITUTION: A sequential fail memory in a defect analytic device 5 is separated into blocks 5b1W5b4 and each block of 5b1W5b4 is controlled by write pulse generators 7aW7d and an address counter which actuate in accordance with each kind of condition described in each of different setting devices 6aW6d, respectively. During a test, a test pattern signal from a generator 1 is supplied to an element to be tested 3 through a programmable data selector 2 and the output signal of the element 3 is compared with an expected value pattern come from the selector 2 in a comparator unit 4 and when a defect is detected, defective data, expected value patterns and pattern counter values are analyzed on the basis of a storage contents of an address fail memory 5a and blocks 5b1W5b4.
COPYRIGHT: (C)1981,JPO&Japio
JP15089479A 1979-11-21 1979-11-21 Testing device for ic Pending JPS5673354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15089479A JPS5673354A (en) 1979-11-21 1979-11-21 Testing device for ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15089479A JPS5673354A (en) 1979-11-21 1979-11-21 Testing device for ic

Publications (1)

Publication Number Publication Date
JPS5673354A true JPS5673354A (en) 1981-06-18

Family

ID=15506696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15089479A Pending JPS5673354A (en) 1979-11-21 1979-11-21 Testing device for ic

Country Status (1)

Country Link
JP (1) JPS5673354A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS585681A (en) * 1981-06-30 1983-01-13 Mitsubishi Electric Corp Testing device for semiconductor memory
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis
WO1998027556A1 (en) * 1996-12-19 1998-06-25 Advantest Corporation Memory test set

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3116819A (en) * 1962-07-16 1964-01-07 Gen Electric Filament loading mechanism
JPS4931075B1 (en) * 1969-11-29 1974-08-19
US3966040A (en) * 1975-03-05 1976-06-29 Hazelwood John E Combined vibratory feeder drive unit, vibratory feeder bowl, and parts separator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3116819A (en) * 1962-07-16 1964-01-07 Gen Electric Filament loading mechanism
JPS4931075B1 (en) * 1969-11-29 1974-08-19
US3966040A (en) * 1975-03-05 1976-06-29 Hazelwood John E Combined vibratory feeder drive unit, vibratory feeder bowl, and parts separator

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS585681A (en) * 1981-06-30 1983-01-13 Mitsubishi Electric Corp Testing device for semiconductor memory
JPH0326480B2 (en) * 1981-06-30 1991-04-10 Mitsubishi Electric Corp
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis
WO1998027556A1 (en) * 1996-12-19 1998-06-25 Advantest Corporation Memory test set
US6061813A (en) * 1996-12-19 2000-05-09 Advantest Corporation Memory test set

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