JPS556201A - Memory device testing method - Google Patents

Memory device testing method

Info

Publication number
JPS556201A
JPS556201A JP7736678A JP7736678A JPS556201A JP S556201 A JPS556201 A JP S556201A JP 7736678 A JP7736678 A JP 7736678A JP 7736678 A JP7736678 A JP 7736678A JP S556201 A JPS556201 A JP S556201A
Authority
JP
Japan
Prior art keywords
addresses
standard
address
jump
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7736678A
Other languages
Japanese (ja)
Inventor
Tomoharu Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7736678A priority Critical patent/JPS556201A/en
Publication of JPS556201A publication Critical patent/JPS556201A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve the trouble detecting ability and to form such test patterns as can shorten the test time by dividing memory addresses into standard addresses and jump priority addresses so that the tests for a preset step are conducted for all standard addresses.
CONSTITUTION: 0(1) is written in all the memory addresses of matrix construction, and the addresses from 0 to the maximum are used as standard addresses. All the addresses excepting the standard addresses of lines and rows including the standard addresses are used as jump priority addresses. 1(0) is written in one of the standard addresses. For each of the jump priority addresses for that standard address, the three steps of the reading operations of the jump priority address 0(1), the standard address 1(0) and the jump priority address 0(1) are accomplished. Finally, they are rewritten into the standard address 0(1). Then, 1(0) is written in another standard address, and similar tests are accomplished. The same tests are accomplished for all the standard addresses in a similar manner.
COPYRIGHT: (C)1980,JPO&Japio
JP7736678A 1978-06-28 1978-06-28 Memory device testing method Pending JPS556201A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7736678A JPS556201A (en) 1978-06-28 1978-06-28 Memory device testing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7736678A JPS556201A (en) 1978-06-28 1978-06-28 Memory device testing method

Publications (1)

Publication Number Publication Date
JPS556201A true JPS556201A (en) 1980-01-17

Family

ID=13631900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7736678A Pending JPS556201A (en) 1978-06-28 1978-06-28 Memory device testing method

Country Status (1)

Country Link
JP (1) JPS556201A (en)

Similar Documents

Publication Publication Date Title
JPS5585265A (en) Function test evaluation device for integrated circuit
JPS5589980A (en) Semiconductor memory unit
JPS556201A (en) Memory device testing method
JPS57131076A (en) Pattern generator for testing high speed lsi
JPS55108999A (en) Check method of ic memory
JPS5558896A (en) Analyzer for memory defect
JPS59101100A (en) Data comparing system
JPS5230123A (en) Time sharing using method of display memory
JPS5436151A (en) Test unit for micro computer system
JPS5673364A (en) Testing device of memory
JPS5320823A (en) Memory unit test system
JPS5698796A (en) High-speed memory test system
JPS5673361A (en) Testing device of ic
JPS5472924A (en) Semiconductor memory inspection equipment
JPS5250689A (en) Checking device for defect of directional pattern
JPS57103199A (en) Memory-package testing method
JPS5266339A (en) Display of memory test results
JPS5673354A (en) Testing device for ic
JPS5641599A (en) Address generation system of pattern generator
JPS524745A (en) Testing method for semiconductor memory device
JPS5694453A (en) Test signal generating device
JPS5771055A (en) Program test system
JPS5431236A (en) State information recorcing system
JPS545632A (en) Test method for memory unit
JPS5357715A (en) Testin device for memory device