JPS5679346A - Diagnostic circuit - Google Patents

Diagnostic circuit

Info

Publication number
JPS5679346A
JPS5679346A JP15667179A JP15667179A JPS5679346A JP S5679346 A JPS5679346 A JP S5679346A JP 15667179 A JP15667179 A JP 15667179A JP 15667179 A JP15667179 A JP 15667179A JP S5679346 A JPS5679346 A JP S5679346A
Authority
JP
Japan
Prior art keywords
scan
memory
register
contents
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15667179A
Other languages
Japanese (ja)
Inventor
Hitoshi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15667179A priority Critical patent/JPS5679346A/en
Publication of JPS5679346A publication Critical patent/JPS5679346A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To shorten the time required for diagnosing an apparatus and simplify the control procedures of the external control device, by adopting a high speed scan-out and the comparison system.
CONSTITUTION: In the memory A1 is stored a data by which the bit corresponding to the scan-out point requiring comparison with the scan-out and the expected value data has been made "1", and in the memory B10 is stored the expected value in this test. In the event of diagnosis, a scan-out data is obtained by making the address register A2 step by "1" under the control of the control circuit 22, reading out the contents of the memory A1, and sending the scan-out address to the apparatus 100 to be diagnosed. It is stored in the shift register 13. After the scan-out has been executed by the prescribed number of times, the memory B10 is read out and is compared with the contents of the register 13. In case when its noncoincidence has occurred, the external control device 101 reads out the contents of the register 13 and the address register B11, and points out the fault position by use of a fault dictionary which has been obtained in advance.
COPYRIGHT: (C)1981,JPO&Japio
JP15667179A 1979-12-03 1979-12-03 Diagnostic circuit Pending JPS5679346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15667179A JPS5679346A (en) 1979-12-03 1979-12-03 Diagnostic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15667179A JPS5679346A (en) 1979-12-03 1979-12-03 Diagnostic circuit

Publications (1)

Publication Number Publication Date
JPS5679346A true JPS5679346A (en) 1981-06-29

Family

ID=15632754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15667179A Pending JPS5679346A (en) 1979-12-03 1979-12-03 Diagnostic circuit

Country Status (1)

Country Link
JP (1) JPS5679346A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59225461A (en) * 1983-06-07 1984-12-18 Fujitsu Ltd Incorporated logic recorder
JPH08320806A (en) * 1995-05-25 1996-12-03 Nec Corp Fault automatic detection system for digital ic

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59225461A (en) * 1983-06-07 1984-12-18 Fujitsu Ltd Incorporated logic recorder
JPH08320806A (en) * 1995-05-25 1996-12-03 Nec Corp Fault automatic detection system for digital ic

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