JPS5674759A - Diagnostic system - Google Patents
Diagnostic systemInfo
- Publication number
- JPS5674759A JPS5674759A JP15208079A JP15208079A JPS5674759A JP S5674759 A JPS5674759 A JP S5674759A JP 15208079 A JP15208079 A JP 15208079A JP 15208079 A JP15208079 A JP 15208079A JP S5674759 A JPS5674759 A JP S5674759A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- diagnosed
- memory
- output data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE: To make it possible to diagnose a circuit to be diagnosed with efficiency by use of diagnostic by using automatically generated diagnostic data by passing data through a memory while considering the memory to be part of a combination circuit.
CONSTITUTION: Automatically generated test input data for a diagnosis is set in input register R1 and the inputted to combinational circuit C1. After the operation of this circuit C1, output data from circuit C1 is written in IC memory ICM. Next, the data written in memory ICM is transferred to the combinational circuit. Output data from this circuit C2 is observed as test output data and, when a previously prepared circuit to be diagnosed is in normal operation, is compared with its correct answer data; when the test output data disagrees with the correct answer data, the comparison result is analyzed to point out the fault position. Thus, the circuit to be diagnosed can be diagnosed with efficiently by using the automatically generated diagnostic data.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15208079A JPS5674759A (en) | 1979-11-26 | 1979-11-26 | Diagnostic system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15208079A JPS5674759A (en) | 1979-11-26 | 1979-11-26 | Diagnostic system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5674759A true JPS5674759A (en) | 1981-06-20 |
Family
ID=15532608
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15208079A Pending JPS5674759A (en) | 1979-11-26 | 1979-11-26 | Diagnostic system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5674759A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS533145A (en) * | 1976-06-30 | 1978-01-12 | Ibm | Method of testing level sensing logical device |
-
1979
- 1979-11-26 JP JP15208079A patent/JPS5674759A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS533145A (en) * | 1976-06-30 | 1978-01-12 | Ibm | Method of testing level sensing logical device |
JPS533754A (en) * | 1976-06-30 | 1978-01-13 | Ibm | Method of testing propagating delay of level sensing array embedded logical device with one side delay dependancy |
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