JPS5694447A - Test system of parity checker - Google Patents

Test system of parity checker

Info

Publication number
JPS5694447A
JPS5694447A JP17082579A JP17082579A JPS5694447A JP S5694447 A JPS5694447 A JP S5694447A JP 17082579 A JP17082579 A JP 17082579A JP 17082579 A JP17082579 A JP 17082579A JP S5694447 A JPS5694447 A JP S5694447A
Authority
JP
Japan
Prior art keywords
checker
test information
area
stored
parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17082579A
Other languages
Japanese (ja)
Inventor
Kanzo Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17082579A priority Critical patent/JPS5694447A/en
Publication of JPS5694447A publication Critical patent/JPS5694447A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To diagnose the checker by the same system as the normal work, by storing previously test information of an abnormal parity state in the memory part specially and by reading this test information for diagnosis of the checker.
CONSTITUTION: The area where test information of an abnormal parity state is stored is provided in memory part MEM of the parity check circuit, and test information is stored in this area previously, and information of the memory area given by address decoder ADD is transmitted to buffer Buff. For diagnosis of the checker, the address of the area where test information is stored is given to memory part MEM from the CPU, and test information corresponding to the address output from decoder ADD is read and is applied to parity checker CH; and if checker CH operates normally, the sum of input information is applied as 1 to register Reg. Contents of register Reg are confirmed by the CPU, and thus, checker CH is diagnosed by the same system as the normal work.
COPYRIGHT: (C)1981,JPO&Japio
JP17082579A 1979-12-27 1979-12-27 Test system of parity checker Pending JPS5694447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17082579A JPS5694447A (en) 1979-12-27 1979-12-27 Test system of parity checker

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17082579A JPS5694447A (en) 1979-12-27 1979-12-27 Test system of parity checker

Publications (1)

Publication Number Publication Date
JPS5694447A true JPS5694447A (en) 1981-07-30

Family

ID=15912022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17082579A Pending JPS5694447A (en) 1979-12-27 1979-12-27 Test system of parity checker

Country Status (1)

Country Link
JP (1) JPS5694447A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59108941U (en) * 1982-12-28 1984-07-23 富士通株式会社 Parity check circuit
JPH0474340U (en) * 1990-11-13 1992-06-29

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59108941U (en) * 1982-12-28 1984-07-23 富士通株式会社 Parity check circuit
JPH0474340U (en) * 1990-11-13 1992-06-29

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