JPS6479792A - Memory - Google Patents

Memory

Info

Publication number
JPS6479792A
JPS6479792A JP62236098A JP23609887A JPS6479792A JP S6479792 A JPS6479792 A JP S6479792A JP 62236098 A JP62236098 A JP 62236098A JP 23609887 A JP23609887 A JP 23609887A JP S6479792 A JPS6479792 A JP S6479792A
Authority
JP
Japan
Prior art keywords
outputs
signal
memory
decoder
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62236098A
Other languages
Japanese (ja)
Inventor
Takeshi Hajika
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62236098A priority Critical patent/JPS6479792A/en
Publication of JPS6479792A publication Critical patent/JPS6479792A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To make it possible to access display data consisting of the prescribed number of bits by one operation by controlling the bit access of two memory planes by a selection means. CONSTITUTION: A decoder 5 outputs one of memory selection signals R, G, B, I in accordance with an address based upon a mode specification signal outputted from a processor, a decoder 12 outputs a bit selection signal in accordance with the selection signal and a decoder 13 similarly outputs a gate signal. Thereby an OR circuit to which one of gate signals X3 to X0 or Y3 to Y0 is inputted out of plural OR circuits 21 to 24 outputs the signal R, G, B, or I to a corresponding memory plane out of plural memory planes 1 to 4. Consequently one of the memory planes 1 to 4 can be accessed.
JP62236098A 1987-09-22 1987-09-22 Memory Pending JPS6479792A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62236098A JPS6479792A (en) 1987-09-22 1987-09-22 Memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62236098A JPS6479792A (en) 1987-09-22 1987-09-22 Memory

Publications (1)

Publication Number Publication Date
JPS6479792A true JPS6479792A (en) 1989-03-24

Family

ID=16995700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62236098A Pending JPS6479792A (en) 1987-09-22 1987-09-22 Memory

Country Status (1)

Country Link
JP (1) JPS6479792A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214360A (en) * 1990-01-19 1991-09-19 Pfu Ltd Image data write processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214360A (en) * 1990-01-19 1991-09-19 Pfu Ltd Image data write processing system

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