JPS6432490A - Control circuit for dynamic memory - Google Patents

Control circuit for dynamic memory

Info

Publication number
JPS6432490A
JPS6432490A JP62187273A JP18727387A JPS6432490A JP S6432490 A JPS6432490 A JP S6432490A JP 62187273 A JP62187273 A JP 62187273A JP 18727387 A JP18727387 A JP 18727387A JP S6432490 A JPS6432490 A JP S6432490A
Authority
JP
Japan
Prior art keywords
signal
gate
control circuit
dynamic memory
high level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62187273A
Other languages
Japanese (ja)
Inventor
Toru Kosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62187273A priority Critical patent/JPS6432490A/en
Publication of JPS6432490A publication Critical patent/JPS6432490A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify the constitution of the whole of a control circuit by sharing a part of a circuit for data read/write and hidden refresh. CONSTITUTION:When a flag signal HF is set to the low level, an AND gate 3 is closed as it is; and meanwhile, a signal RAS is outputted from a NOR gate 6 because an AND gate 2 is opened only when a signal t1 is in the high level and a signal t2 is in the low level. When the flag signal HF is set to the high level, the signal RAS is outputted from the NOR gate 6 because the AND gate 3 is opened when a signal t3 is in the high level and a signal t4 is in the low level. Thus, the signal RAS used for data read/write and hidden refresh is generated with the simple circuit of opening/closing of one AND gate 3.
JP62187273A 1987-07-27 1987-07-27 Control circuit for dynamic memory Pending JPS6432490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62187273A JPS6432490A (en) 1987-07-27 1987-07-27 Control circuit for dynamic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62187273A JPS6432490A (en) 1987-07-27 1987-07-27 Control circuit for dynamic memory

Publications (1)

Publication Number Publication Date
JPS6432490A true JPS6432490A (en) 1989-02-02

Family

ID=16203105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62187273A Pending JPS6432490A (en) 1987-07-27 1987-07-27 Control circuit for dynamic memory

Country Status (1)

Country Link
JP (1) JPS6432490A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729399U (en) * 1993-12-24 1995-06-02 三菱重工業株式会社 Split type heat insulation device for nuclear power plant piping

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729399U (en) * 1993-12-24 1995-06-02 三菱重工業株式会社 Split type heat insulation device for nuclear power plant piping

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