JPS5622286A - Dynamic memory control system - Google Patents
Dynamic memory control systemInfo
- Publication number
- JPS5622286A JPS5622286A JP9777879A JP9777879A JPS5622286A JP S5622286 A JPS5622286 A JP S5622286A JP 9777879 A JP9777879 A JP 9777879A JP 9777879 A JP9777879 A JP 9777879A JP S5622286 A JPS5622286 A JP S5622286A
- Authority
- JP
- Japan
- Prior art keywords
- address
- refresh
- signal
- memory cell
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To enable the readout/write-in always stable even with noise, by performing the refresh of memory cell through the forming of address signal exclusively used for the refresh based on the address nonselection signal. CONSTITUTION:Normally, the control circuit repeats the memory access and nonaccess, and at memory access, in synchronizing with the address selection signal of the said memory cell chip, readout/write-in is made. If the control circuit is at nonmemory access and the memory is not selected, a signal is given to the FF-D1 via the NAND gate NA2 and inverter IN2 and output is produced in synchronizing with the clock phi4 to form the address strobe RAS2 with the NAND gate NA3 and inverter IN3, and this becomes the row address strobe RAS2 via the NOR gate NR. In this case, no column address strobe CAS is produced, and the memory cell is in refresh state. Further, repetitive refresh operation is made.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9777879A JPS5622286A (en) | 1979-07-30 | 1979-07-30 | Dynamic memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9777879A JPS5622286A (en) | 1979-07-30 | 1979-07-30 | Dynamic memory control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5622286A true JPS5622286A (en) | 1981-03-02 |
Family
ID=14201281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9777879A Pending JPS5622286A (en) | 1979-07-30 | 1979-07-30 | Dynamic memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5622286A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63166093A (en) * | 1986-12-26 | 1988-07-09 | Toshiba Corp | Control circuit for semiconductor memory |
-
1979
- 1979-07-30 JP JP9777879A patent/JPS5622286A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63166093A (en) * | 1986-12-26 | 1988-07-09 | Toshiba Corp | Control circuit for semiconductor memory |
JPH059877B2 (en) * | 1986-12-26 | 1993-02-08 | Tokyo Shibaura Electric Co |
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