JPS60157798A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make high-speed and continuous burst transfer possible by providing an independent row address signal latch circuit for every memory cell array and latching the row address of the second array in said circuit while the first array is accessed. CONSTITUTION:Row address signal latch circuits 501 and 502 independent of each other are provided for the purpose of giving row address signals 411 and 412 to row decoders 401 and 402 respectively, and row address signals are given to circuits 501 and 502 through row address latch signal lines 511 and 512 respectively. A column address signal 721 is given to a column decoder 200 from a column address signal latch circuit 700 through a signal line 711. The circuit 700 has a precedence determining circuit for data busses 301 and 302. Thus, when the k-th row is accessed following a period R1 of access to a specific j-th row, the data bus 301 is inactivated but the data bus 302 is activated at a time T9 by the precedence determining circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory capable of high-speed access.

[Technical background of the invention]

FIG. 1 is a timing diagram showing the operation of a conventional dynamic random access memory. In conventional dynamic random access memory, Nutateik random access memory, read-only memory, etc., generally when selecting a specific memory cell, the cycle time t of access in the column direction within the same row. The cycle time t, which includes different inter-row accesses compared to 1. 2 had the drawback of being slow. In FIG. 1, a period τ1 is an access period for a specific fifth row, and a period τ2 is an access period for a specific fifth row.

In the access period for the fifth row, tcl represents the cycle time for accessing a different column, and jc2 represents the cycle time for accessing a different column from the fifth row. Therefore, jc2 jc1=trp+t8+tcp. Here trp>tcp so tc2>tcl
becomes. Note that trp is the sense system precharge time, t
s is the sense time, and tcp is the column-based grid charge time.

[Problems with background technology]

However, in such a case, the cycle time t between incoming rows is smaller than the cycle time tc1 between the same rows. 2
is long, so it takes a long cycle time t to synchronize during continuous data transfer such as burst mode transfer.
02, and the short cycle time tc1 cannot be used effectively. In other words, the system has a long cycle time t. It is necessary to perform burst mode transfer to synchronize with 1.

In order to effectively operate the system with a short cycle time tc1, it is necessary to provide a semiconductor memory twice the desired memory capacity, form a two-bank memory configuration, and perform an interleaved operation on these. However, in such a configuration, the maximum memory capacity of the system is 2
The problem is doubled.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a semiconductor memory capable of performing continuous high-speed access between two memory cells between different rows, thereby performing high-speed and continuous burst transfer. There is a particular thing.

[First aspect of the invention] The present invention provides a plurality of memory cell arrays, and each memory cell array has a first memory cell array. The present invention is characterized in that an independent row address signal latch circuit is provided to latch the row address of the second memory cell array to the row address signal latch circuit while the first memory cell array is being accessed.

[Embodiments of the invention]

A practical example of the present invention is shown in FIG. 2 below.

This will be explained in detail with reference to the drawings. 101° no 02 in the diagram
are the first. In the second memory cell array, each memory cell array 101, 102i has a data bus 301.
, 302 are provided.

And the first. A column decoder 2θ0 is provided to select any column of the second memory cell array. Also number 1. Sense amplifier rows 601 and 602 are provided in the second memory cell arrays 101 and 102, respectively, and row decoders 401 and 402f are provided in each of the second memory cell arrays 101 and 102 to select an arbitrary row of the memory cell arrays 101 and 102, respectively. and each row decoder 401.4
Row address signal latch circuits 5ol are used independently of each other to provide row address signals 411 and 412 to 02, respectively.
* 50 "l:ttsE' is applied.The row address signal latch circuit 50 is given a row address signal via the row address latch signal line 51, and similarly, the row address signal latch circuit SOZ is given a row address signal. A row address signal is applied via a latch signal line 512.

A column address signal 72 is then applied from the column address signal latch circuit 700 to the column decoder 200 via a column address launch signal line 711.

The column address signal latch circuit 7θ0 has a priority circuit that activates one of the data buses 30 and 3θ2 and deactivates the other in accordance with the priority.

The data buses 901 and 302 each transfer data via the data input/output circuit 800. It has a data input/output circuit 800 (ri, data input terminal 80) and a data output terminal 8θ2.

Furthermore, -17 troll circuits 901, 902, 903, and 904 are provided in the clock control circuit 90Q.

A first row address strobe signal RASJi is applied to the control circuit 907 via the output signal 91, and a row address latch signal is sent from the control circuit 90 to the row address signal latch circuit 501 via the output signals i and 511f. Output. Similarly, the control circuit 9θ2 has a row address strobe signal RAS 2k, which is connected to the control circuit 9θ2.
A row address latch signal is output from the control circuit 902 to the row address signal latch circuit 502 via the output signal line 512f. The control circuit 90.9 receives an output signal line 921 of the control circuit 901, an output signal line 922 of the control circuit 902, and a column address strobe signal line 913 from the outside, and via the column address latch signal line 711, Column address signal output circuit 700. A column address signal is given to the data input/output circuit 8oθ. Furthermore, a column address signal is supplied to the control circuit 904 via a column address latch signal line 711, and an external input &'
A write enable signal section is applied to the data input/output circuit 8θ0 via a read/write control signal line 924.

In such a configuration, the operation is performed as shown in the timing chart shown in FIG. In other words, RAS 1 changes from H level to L level.
Time T to transition to level. During the period R71d from to time T at which the L level transitions to the H level, the memory cells in the first row of the first memory cell array are selected based on the row address latched at time T0. And R.A.S.
After time T8 when 2 transitions from H level to L level,
Time T when RAS1 transitions from L level to H level
, during the subsequent period R2, the first row of the second memory cell array is selected based on the row address latched at time T8.

Then, at time T1, the column address is latched by CAS, and at time T2, the data output Dout becomes valid at column address access time TCAC. After that, the column address is similarly latched by CAS at times T3 and T, and the data output Dout becomes valid at times T4 and T6, respectively. Therefore, the cycle time for access within the same row, for example within the first row, is T. It becomes 1.

Further, in the above embodiment, it is possible to select row ik of the second memory cell array to be selected next while keeping the first row of the first memory cell array selected by RAS1. That is, when RAS2 falls at time T8, the address signal A1 is latched into the row address signal latch circuit 502,
The row address decoder 402 is activated, the first row of the memory cell array 102 is activated, and the in-memory gk sense amplifier row 602 of the second row senses and occupies i so. In this case, the column address signal latch circuit 700 prioritizes the data paths 30 in the circuit.

One of 302 can be activated and the other is deactivated.

For this purpose, a control signal is provided through column address signal latch circuit 70θ (output line 93 of control circuit 901) and output line 932 of control circuit 902.

Therefore, RAS , 1 , RAS given from the outside
2 are both at low level, these signals RAS and R
While the data bus corresponding to the memory cell array on the side of AS2 that first becomes low level can be activated, the other data bus remains inactive. Also RAS J, RAS
When only one of 2 is low level, the data bus corresponding to the memory cell array on the low level side can be activated.
, the other data bus becomes inactive.

In this way, for example, as shown in the timing diagram shown in FIG. 3, when accessing a specific first row following the access period R, the priority order is determined by the circuit. At time T, the data bus 301
is deactivated, and data bus 302 can be activated.

That is, the second row of the second memory cell array has already been activated since time T8, and the data bus 302 has been activated since time T8.
, it becomes possible to activate it. Therefore, the cycle time Tc2 as a period from the time T7 when the data in the first row becomes valid to the time T1 when the data in the second row becomes valid is compared to the cycle time Tc1 required for accessing the same row. It can be equal or shorter.

Note that the configuration shown in FIG. 2 can be integrated into a single LSj chip, which is extremely preferable since productivity is good and handling is easy.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to configure it as a single integrated λrf circuit element, and the cycle time Tc2 of accesses between different rows is greater than the cycle time Tc1 of accesses in the same row in the same continuous row. is equal to or
Can be shortened. Therefore, even when performing high-speed burst mode transfer, there is no need for a two-pan memory configuration, which reduces the amount of memory in the system. Semiconductor memo that can be halved and reduce costs

[Brief explanation of the drawing]

FIG. 1 is a timing diagram showing the operation of a conventional dynamic random access memory, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram showing the operation of the dynamic random access memory of the above embodiment. It is. 101.102...Memory cell array, 2θ0...
Column decoder, 301.302...Data bus, 401
．． 402... row decoder, 50.1, . 502...
・Row address signal latch circuit, 601, 602...Sense amplifier row, 700...Column address signal latch circuit, SOO...Data input/output circuit, 80...Data input terminal, 802...Data Output terminal. Carving 1 Fig. To - - ~ γ1
to t+ tzt3tctst6t7tats t+
otnt+z tn t+4tst+6t+7 2nd F2
J...'' Figure 3 R1 r:? . D.

Claims (1)

[Claims] A plurality of memory cell arrays in which memory cells are arranged in rows and columns, a row decoder for row selection provided in each memory cell array, a column decoder for column selection provided in each memory cell array, and a corresponding row decoder provided for each row decoder. 1. A semiconductor memory comprising: a row address signal latch circuit that applies an address signal to a memory cell array and latches an address signal for a memory cell array that is not being accessed while a specific memory cell or array is being accessed.