JPS5891590A - Memory system - Google Patents

Abstract

PURPOSE:To input and output a data at a high speed, by applying the first clock for giving activation and an address signal, to plural memory elements which use data input and output lines in common, and also applying the second clock for giving an input/output control time difference of a data. CONSTITUTION:A pair of memory elements M1, M2 use in common a data input line DIN, an output line DOUT, a chip enable line CE and an address line Add. When the first clock CE becomes L from H, the elements are activated, and also input an address signal, too. When the second clocks IOE1, IOE2 are applied to the input/output controlling circuit by shifting the timing, while the clock IOE1 is L and an output OUT1 is sent out to the data output line from the element M1, the other clock is H, and an output of the element M2 is held at high impedance. When said operation is executed alternately, the selecting time of the element is eliminated, and input and output operations of a data are executed at a high speed.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a method for connecting a plurality of memory elements (herein ζ refers to a memory unit comprising a large number of memory cells and their peripheral circuits) to a common data line. Regarding the memory system,
This is intended to speed up data input/output by simultaneously selecting two or more memory elements and performing data input/output in a time-division manner.

(2) Background of the technology When multiple memory elements are connected to a common data input/output port IIIK to configure one memory system, at the time of data input/output #'i1 between the system and the outside, only one memory element is connected. Since the number of available memory devices is limited, it is necessary to select a memory device each time data is output to the system. The time required to select this memory element limits the data input/output speed.

(3) Prior art and problems) In conventional memory systems, data is output only once (
When the input (or input (hereinafter, input is omitted) is completed, the above-mentioned memory element selection operation is always interposed between the next data output and the lower limit of the interval between data sequentially output on the same data line. is limited by the selection time of this memory element, and cannot be shortened unless the operating time of the memory element itself is improved.

(4) Purpose of the Invention The present invention aims to increase the speed of data input/output of a memory system by controlling the memory elements even if the same operating speed is used.

(5) Structure of the Invention The basic structure of the present invention is that a plurality of memory elements each having a built-in memory cell array and its peripheral circuits are connected to a common data source.
In a memory system configured by connecting to an output line,
Commonly applying a first clock having a function of activating the memory elements and an address signal to the plurality of memory elements, and then applying a second clock having a control function to cause input/output to each memory element at different timings; It is characterized in that data input and output are performed in a time-sharing manner through data input and output lines.

(6) Embodiments of the invention Hereinafter, the invention will be explained in detail with reference to the illustrated embodiments. FIG. 1 shows a basic embodiment of the present invention, in which MleMl is a pair of memory elements connected to common data input/output lines, address lines, and control lines such as chip enable to form one memory system. do. As a memory system, a memory element M' belonging to the same column as memory element Ml
, , M#, , −・−・・and memory element M! The memory element M'tomi belonging to the same column as .

M',, -...-, and the data output line etc. may be provided as many as the number of memory elements belonging to the same column to increase the capacity. Of course, the number of paired memory elements is not limited to two but three. In this case, the memory elements are configured on one chip, and multiple chips constituting the memory system are housed in a package to form one integrated circuit. do. Furthermore, as a memory element, a static type is assumed first. In the following, explanation will be mainly limited to the memory element pairs Reiou and Shima, and both of them are equipped with a timing generation circuit τG1 memory cell array MCA, an input/output control circuit IOC, and the like.

The paired memory elements M,,M, are connected to the data input line D! summer,
Data output II! DaIJ! , chip enable (first
CE1 address line Add is made common.

Although there is one address line dd in the drawing, there are actually a plurality of lines depending on the number of bits of the address.

Input/output enable (second clock) @IoB,.

IOE, #'i Conventional method requires only one element, M, , M
, if stored in a common package, each chip's ITO
The E pad is commonly connected to the 10IC bin of the package, but is provided for each memory element M1eM1 in the present invention.

FIG. 2 is an operating waveform diagram. When the clock CE of 1IL1 goes from H (high) to L (ct-)K, the memory element area and dovetail are activated (selected) at the same time.This clock CE not only activates the element, but also its falling edge corresponds to the address signal signal. dd
K) is also used. Since the address signal Add is common to memory elements 1N, , M, each memory element M
1. M, attempts to output data from the same location on the memory cell array MC. However, in this case, the data output line I
) out is shared by wired or, so the output is 0U
T1. OUT conflicts, so input/output control/
Second clock l01i1e l0 that adds circuit l0CK
The timing of It is shifted as shown in FIG. In this way, when the clock IOE is L, the output OUT from the memory element M becomes the data output line DW? while being sent to other °
Oriental Ptsuku I01. is H and the output OU of memory element M is
T, is kept high impedance, and the clock I 0
1. becomes L and the output OU'r becomes the data output aDoυ
! During the period when the clock IOΣ is sent to H, the output OUT of the memory element M1 is kept at high impedance, so that the output 0UT1 . OU'r, is the data output @Do
There is no conflict on or, and there is a Kd time difference between the rise of IOE and the fall of IOE.
Since the L level of the output data and the IOE and OL levels do not overlap, the output data OUT and OU
T.

are reliably separated.

In this way, the data output 11 from the memory element Mimk
The interval between the outputs OUT, , OUT, which are read out during 1Do conversion is shortened as much as possible since there is no mesori element selection time in between. ttb Conventionally, the memory element M turtle.

The first clock C'E for M8 is independently small, 0.
If you want to take out UTI and OU'rt, first activate the memory element with clock CI and take output 08)
OUT, and then set the resistor n to memory element M to L to take out the output OUT. Therefore, the time interval between OUT, OUT, on the data output line T cannot be shortened. On the other hand, in the configuration shown in #r1, the second clock l0E1. By shortening the time difference between IOE, as much as possible, OU'l',, O on the data output line Dotry
The interval between UT and UT is reduced. Note that the address signal Ad in FIG.
@Vallt' in d indicates that during this period, the potential of the address signal line is made stable according to the address signal, making it possible to reliably capture the address, and there is a fall of 1 at approximately the center of this period. )~ @Don't Car@”
indicates that the address signal line potential may fluctuate since address fetching has been completed. Furthermore, although reading has been described above, writing is also the same as reading.

Furthermore, considering a large capacity memory system, each column is made up of multiple memory elements as described above, and the data input/output line DI
NI Dovt each memory element pair (Mt m k & )
* Independently provided for each (M't + M's). and the other clock @CE and address line A for
dl is common and each memory element pair operates in parallel at the same time.

When the memory is a dynamometer, there are usually two types of clocks: 8m8 (low address strobe bar) and CAB (column address strobe bar). When the address line dd is used as a multiplexer that uses the Row (lower) address and C@ltIma (upper) address for time division, the highest QKR
A8 takes in the lower address, then CAS takes in the higher address, so cod i,ko&8t'1jlil:1
It often has the functions of CI and IOH shown in the figure. Therefore,
If the memory system is composed of dynamic RAM elements, replace the first clock from CI with RAS, and change the second clock from I OE @ * I OE m to CA3.
1. In place of CA8m, the configuration of the memory element, I[C
The present invention can also be implemented in the case of a dynamic memory without changing the external terminals or the like. The timing relationship of various signals in this case is shown in Diagram 3.CAB, CAB嘗 has not only the input/output control function of IOEm, but also the original activation and address capture functions, so the third A8 with k as shown in the figure. Even if the upper address is captured at the falling edge of CAB, output 08, OUT,
does not occur, and a time delay tchc occurs during that time. For this reason, CAS.

CAB has a wider time width than Ioe in Figure 2, the upper address determination period (upper Vald) is longer, and KC is set so that oty'r, OUT do not overlap.
Consideration must be given to AS*-CAB, such as delaying it more fully.

Figure 4 is an explanatory diagram of the external terminals of a normal dynamic memory element, where Y@s and Vs@ are power supply terminals, Add
is an address terminal (one K), RA8. CAB, WE are control terminals (WE is write enable), IN,
OUT is an input/output terminal. If the control method shown in Fig. 3 is used, the normal dynamic memory element shown in Fig. 4 can be used to
The system shown in the figure can be configured. However, if it is allowed to add the control terminal I01 as shown in FIG. 5, RA8. C
When the address is read at AB, the sense amplifier of the dynamic memory takes an output state according to the stored data, and the IOE controls whether or not to output it, so the delay time tchc in Figure 3 is No consideration is required. Figure 6 is a detailed diagram showing the inside of the memory element shown in Figure 5. RD is the lower address latch decoder (ROW), CDFi is the upper address latch decoder (COLUMN), and the other parts are the same as in Figure 1. be. In the multiplex type, the address line Add is common to the lower and upper sides, so the timing control circuit TEG is externally connected to the address line RA8. Decoders RD and CD after receiving CAS
[Instructs to import address.] The memory element shown in FIG. 4 does not have an external terminal corresponding to IOE, and the input/output control circuit IOC takes in the CAS internally and controls the output using this.

For this reason, consideration must be given to the delay time tcic as described above, but a second clock control terminal IOE independent of the input/output control circuit IOCK is provided (in this case, the l0C4DCA8 terminal is connected to the skeleton IOE terminal). ), the number of external terminals increases, but the output can be controlled at the timing shown in FIG. In the same figure, l03el and IOE* represent the memory element pair M1. M, and its time relationship is Kfi as in the g2 diagram. That is, the defeat and activation of the lower address is performed by one of the clocks of Rattan 1, RAS, and the capture and activation of the upper address is performed by the first clock.
Since the other one of the clocks is CAS, there is no need to extend the upper address, and l0El, IOE.

There is no need to include the width KtcAc.

It is easy to decide whether to use the control method shown in Figure 3 or the control method shown in Figure 7 for the dynamic memory, and no major circuit changes are required. Since the internal configuration in Figure 5 is common, the pad PD for CAS on the semiconductor chip CHP, @ in Figure 11c10,
In addition, pads PD for KIOE are formed, and if the memory element shown in FIG. It is sufficient to bond to the CAS terminal, and in the case of the memory element shown in Figure 5, the arrangement tIa is not provided and the pad PD1. It is sufficient to bond each PDtf independently to the CA8 terminal and IOE terminal, and no change is required to the internal wiring or the like.

FIG. 8 is an explanatory diagram when the nibble operation is used in conjunction with the control method shown in FIG. 93 as an example. The nibble operation is an operation in which one address is given, τ7j is set to H or L, and data is sequentially read out from a plurality of addresses related to the address, for example, four or more addresses that are in contact with lI. When the applied CAS is changed as shown in Figure 8, the upper address is taken in at the first fall of CAS, and data D is read out to tcacil in Figure 3 (this is the externally applied data). (corresponding to the address), then the next KCA8 凰 H, L, H, L...-
For example, when changing the L level for the second time, the data island at the address next to it becomes the data island, and at the third L level, the data island Ds at the address next to it becomes 4, etc., without changing the address given from the outside. The data D1 to D4 are sequentially read out. Here, the control method shown in Fig. 3 is introduced, and the CA of the memory element kliFc is shifted by a half cycle (one cycle is 10 to 15 ■).
When S is given, the same pressure is applied and the data DI e DI...
Data "SID'@," respectively between...
...-- is read out.

Figure 9 is an explanatory diagram when interleaving is used together.
MGl, , MGl, meeting -m-・MG 鵞1
1MG! !嘗-7 is a memory element array consisting of N memory elements each. Following each column described above, the memory element column MGI& is, for example, the memory element Ml g of FIG.
The interleap ti as shown in FIG. As shown in FIG. 2, there is a free time between when RAS becomes LK and when the data output line Doot [data OUT] actually appears, so we try to make use of this time, and the memory element rows MG□, MQl, , -- ---・ is the first
clock cg1 (RAS for dynamic type.

), the other memory element array M N data outputs using address lines in hours and minutes mK.
Share Dont. When the present invention is applied to this system, each memory element column MGn*MGIIK is directly connected.

IOE, and the memory element rows MG□ and MG□ are further given timing deviations of 9l0Kg and l014t”
During the blank period until OUT in FIG. 3 is read out, other memory element columns can be read out.

For example, in the methods shown in FIGS. 5 and 8, cry is used.

Although the above explanation mainly concerns reading, the same applies to writing. When the write enable terminal WE shown in FIG. 6 is set to ■, reading is performed, and when it is set to L, writing is performed.

g) Effects of the Invention As described above, according to the present invention, a plurality of memory elements shared by a data input/output line are activated simultaneously, and data input/output control is controlled with a time difference. This has the advantage of faster input/output (improved data rate).

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of the present invention, FIG. 2 is an operating waveform diagram thereof, FIG. 3 is an operating waveform diagram showing another embodiment of the present invention, and FIGS. 4 and 5 are 6 is a detailed diagram of FIG. 5, FIG. 7 is an operation waveform diagram showing different embodiments of the present invention, FIG. 8 is an operation waveform diagram using nibble operation, and FIG. FIG. 9 is a schematic configuration diagram using interleaving, and FIG. 10 is an explanatory diagram of a control signal pad common to the memory elements of FIGS. 4 and 5. In the figure, Ml, h are memory signals, DI)l is a data input line, Dot+t is a data output line, CE, RAS, CA
S. IOE is a control signal (terminal), AddFi address signal (
line). Applicant: Fujitsu Limited, Representative Patent Attorney Minoru Aoyagi 1, 2, 011T, 0IIT. Figure 3 Figure 4 Figure 5 Umako Figure DQUT %l 1d
Vutrd Horse 9 Father

Claims (1)

[Claims] (11) In a memory system configured by connecting a plurality of memory elements each having a built-in memory cell array and its peripheral circuitry to a common data line and an output line, A first clock having a control function and an address signal are commonly given, and then a second clock having a control function of inputting and outputting each memory element at different timings is given to the data terminal and the data terminal through the output line. , the memory system is characterized in that the output is performed in a time-divisional manner. (2) The first clock is a row address stop loop signal RA8 having a function of fetching a lower address, and
Claim 1, characterized in that the IX2 transfer signal is a prime address strobe signal Cm8 having a function of receiving an upper address, and these signals are time-divisionally transmitted through the address line. Memory system described. (3) The memory element is an element that performs a nibble operation based on the CA8 signal), and is configured such that each of the CA8 signals, which change in high and low levels with a mutual phase shift, is input to the plurality of memory elements. The memory system according to claim 2, characterized in that: (4) A plurality of memory element groups are provided whose data output is time-divisionally performed using a second clock, and each group is anisotropically arranged so that the first clock output data is interleaved. The memory system according to claim 2 or 3, characterized in that the memory system is provided with a