JPS621182A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To access continuously memory cells at a high speed without an address skew in mind by permitting an address signal formed by a built-in address counter circuit to switch row and column addresses. CONSTITUTION:When a clock signal, the inverse of CL and a chip selecting signal, the inverse of CS supplied through an external terminal are made at a low level, an internal control signal generator circuit TG makes an internal chip selecting signal at a high level to fetch an address signal supplied through an external terminal. Then said circuit TG changes a control signal (mx) at a low level, and fetches it to an address counter circuit COUNT with the fetched address signal as an initial value. The output signals ax' and ay' of the address counter circuit COUNT are selected, transmitted to an address decoder, and are simultaneously made in the selection state by word line selection timing signals phix1 and phix2 simultaneously generated by word lines at both sides. At the time the action timing signals phipa1 and phipa2 of sense amplifiers SA1 and SA2 are generated.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in dynamic RAM (random access memory).

[Background technology]

The column selection circuit is configured with a static type circuit,
A dynamic RAM that performs continuous read/write operations of memory cells coupled to the word line by changing the column address signal and switching the data lines one after another while keeping the word line in the selected state.
is being developed. In such a continuous read operation in the static column mode, address switching in the column system is performed by an address signal supplied from an external terminal. In this case, high-speed operation cannot be achieved due to the skew (timing difference between address signals) of the address signals supplied from the external terminals. That is, the column selection operation is performed after waiting for the address signal that changes the slowest among the multi-bit address signals. In addition, the number of consecutive read bits is 1
It is limited by the memory cells coupled to the main word lines. Therefore, for example, it is difficult to use it as a graphics memory for drawing high-definition images at high speed.

Regarding the dynamic RAM, see, for example, the Nikkei McGraw-Hill magazine, Nikkei Electronics J, July 18, 1983, pages 169 to 193.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that can read arbitrary multiple bits at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an address counter circuit is provided which takes in an address signal supplied from an external terminal as an initial value in accordance with an operation mode signal specified by a predetermined external control signal, and performs a walking operation using a pulse supplied from an external terminal.
An address signal formed by the address counter circuit according to the operation mode signal is transmitted to an address decoder through a multiplexer, and one of the columns in the divided memory array is selected according to the address signal formed by the address counter circuit. When the selection of the final address of the memory array is completed, the column selection operation of the other memory array whose word line has already been selected is performed, and the word line selection operation of the next address is performed for the one memory array mentioned above. It is.

〔Example〕

Figure 1 shows a dynamic RA to which this invention is applied.
A block diagram of M is shown. Circuit elements constituting each circuit block in the figure are formed on a semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In this embodiment, the memory array is arranged in two parts, M-ARYl and M-ARY2, although this is not particularly limited. Each memory array M-ARYI, M-
In each of ARY2, the column system (data line) signal line consists of a pair of complementary data lines arranged in parallel, and the two pairs of complementary data lines are set as one set, and in the figure, they are arranged so as to face in the horizontal direction. It is constructed using a two-intersection method. Further, a pair of common complementary data lines CDI and CD2 are arranged, which run vertically to the left and right, respectively, centering on the column decoder C-DCR. Thereby, the column switch circuits C-5WI and C-5W2, which connect the complementary data line and the common complementary data line, connect the complementary data line and the common data line corresponding to each address.

Common complementary data line pair CD1. CD2 is coupled to main amplifiers MAI and MA2, respectively. The column decoder C-DCR decodes an address signal as described later and synchronizes with the data line selection timing signal φy, and the column switch circuits C-3W1. Forms a selection signal to be supplied to C-3W2.

Row-related address selection lines (word lines, dummy word lines) are formed so as to extend vertically in each of the memory arrays M-ARYI and M-ARY2, and are arranged vertically in the figure.

During a write/read operation, sense amplifiers SAI and SA2 are selectively activated by a timing signal φpaLφpa2, and a minute read voltage from a memory cell coupled to one data line is applied to a dummy by a word line selection operation. The complementary data line is amplified to high/low level by referring to the reference voltage from the dummy cell coupled to the other data line by the word line selection operation.

Although not particularly limited, address buffers R and C-ADB are rows (rows) each consisting of a plurality of bits supplied from an external terminal in synchronization with an internal control signal (not shown) formed based on a chip selection signal C8. X) Address signal A
Take in the X, column (Y) address signal AY. These address buffers R and C-DCR are provided with a multiplexer circuit at their output portions, although not particularly limited, and receive address signals AX and AY supplied from the external terminals or address signals formed by an address counter circuit C0UNT to be described later. internal complementary address signals 0 to xm, :Lo-zn corresponding to "ax', ay" are formed.In the following description and drawings, a pair of internal complementary address signals, for example, an address supplied from an external terminal, is formed. Signal XO
Alternatively, the internal address signal xQ having the same phase as the address signal xO'' formed by the address counter circuit C0UNT and the address signal xQ having the opposite phase will be expressed as an internal complementary address signal 50. Therefore, the internal complementary address signals xO to xm , xQ to xm are internal complementary address signals x
These two address signals x shall be denoted as O~Xm.
O-5m and 10 to Ln are sent to the next row address decoders R-DCRI, R-DCR2 and column address decoder C-DCR.

The row address decoders R-DCRI and R-DCR2 are
The above address signals 50 to 5m are decoded to form a word line selection signal, and word line selection timing signals φX1 and φ
Memory array M-ARY 1 and M-AR in synchronization with x2
A selection operation is performed for one word line of Y2 and a dummy word line.

The column address decoder C-0CR decodes the address signals i0-n and outputs the data line selection timing signal φ.
Memory array M-ARYI or M-ARY in synchronization with y
2 data line selection signals are formed.

The column switches C-5WI, C-3W2 receive the selection signal formed by the column address decoder C-DCH, and select the complementary data lines in the memory array M-ARY1 or M-ARY2 from the common complementary data CDI, CD2. be connected to each.

Main amplifier MA1. MA2 is the timing signal φma
1 and φtaa2, and performs an operation of amplifying the signals read out to the common complementary data lines CDI and CD2.

The input/output circuit I10 includes a data output buffer for reading and a data manual buffer for writing. In the case of a read operation when the write enable signal WE is at a high level, the data output buffer is activated at a predetermined timing, amplifies the output of the main amplifier MAL or MA2, and sends it to an external terminal. In a write operation in which the write enable signal WE is set to a low level, the data manual buffer is activated at a predetermined timing and transmits write data to the common complementary data lines CDI and CD2 (not shown).

The internal control signal generation circuit TG is not particularly limited, but may be 4
It receives external control signals C3 (chip selection signal), OE (output enable signal), WE (write enable No. 48), and CL (clock signal), forms and sends out the above various timing signals necessary for memory operation. .

FIG. 2 shows a circuit diagram of one embodiment of the above-mentioned atto 1/sub 7 buffer and address counter circuit.

In the figure, a representative unit circuit of an address buffer for 1 bit is shown. That is, the address signal supplied from the illustratively shown external terminal A Y n is the internal chip selection signal. Nando (controlled by
P-channel MOS F, which is one input terminal of the next multiplexer circuit, via the NAND) gate circuit G1.
It is supplied to E T Q 3 and the gate of N-channel MO5FE'rQ4. Above P channel MO3I”ET
A control signal m is connected between the source of Q3 and the power supply voltage Vcc.
A P-channel MO5FET QI receiving x is provided;
Between the source of the N-channel Mo5FET Q4 and the ground potential point of the circuit, there is an N-channel Mo5FET Q4 that receives a control signal;
o5FETQ2 is provided.

P-channel MO5FETQ7 and N-channel MO3FETQ, which are the other input terminals of the multiplexer circuit above.
An output signal yn' corresponding to the external address signal AYn of the address counter circuit C0UNT is supplied to the gate of B. These MOSFETQ? , P-channel Mo5FETQ5 and N-channel M similar to the above are also used for QB.
o8FETQ6 is provided respectively. These MOS
FETQ5. The Q617+ gate is the MO3FE'r
Q1. By being cross-connected to the gate of Q2, the control signals mx and mx are supplied complementary to each other.

The output terminals of the above two circuits are commonly connected and connected to the input terminal of the CMOS inverter circuit IVI. An inverted internal address signal 7] is sent out from the output terminal of this inverter circuit IVI. The output signal of this inverter circuit IVI is supplied to the input terminal of a CMOS inverter circuit IV2, and a non-inverted internal address signal yn is sent from the output terminal of this inverter circuit IV2.

The address counter circuit C0UNT includes a flip-flop circuit FF0=FFn(Y) and FFO arranged in cascade.
-FFm(X) and each flip-flop circuit F
Corresponding internal address signals yo-yn and xO-xm are supplied to set inputs of FO-FFn and FFO-FFm via gate circuits. These gate circuits are controlled by the control signal MOM. As a result, the address signal yn, etc. supplied from the external terminal while the control signal 1 is at a high level is taken into each flip-flop circuit as an initial value. Further, a pulse φ formed based on the clock terminal CL is supplied to the counting input of the first-stage flip-flop circuit FFO that forms each address signal of the column system (Y). The carry signal is the next stage FF
A binary counter operation is performed by being supplied to the stitch number input of L. The carry signal ca of the flip-flop circuit FFn that forms the address signal yn of the most significant bit of the column system counter circuit is the same as the carry signal ca of the flip-flop circuit FFn of the first stage of the counter circuit with a similar configuration that forms each address signal of the row system (X). is supplied to the count input of the input circuit FFO.

Next, a continuous read operation using an internal address signal (hereinafter referred to as extended serial access mode in the present invention) will be explained with reference to the timing diagram shown in FIG.

When the clock signal CL supplied from the external terminal is first changed from high level to low level and then the chip selection signal C3 is set to low level, the internal control signal generation circuit TG determines that this is the extended serial access mode. The following timing signals are generated. First, the internal chip selection signal cs is set to a high level (not shown) by the low level of the chip selection signal C8O, and an address signal supplied from an external terminal is taken in. After that, the control signal mx is changed from high level to low level, the address signal taken in is taken into the address counter circuit C0UNT as an initial value, and the multiplexer circuits included in the address buffers R and C-ADB are switched, Address counter circuit C0UNT
output signals ax' and ay' are selected and transmitted to the address decoder.

For example, memory array M-ARY 1 and memory array M
-ARY2 has a column address of θ~1023
Then, row addresses are assigned like 0 to 511,
If the storage capacity is approximately 1 Mbit in total, the row address aX" as the initial value is the address 3 assigned to the left memory array M-ARY1.
In the extended serial access mode, the corresponding word line and the word line corresponding to address 4 of the right memory array M-ARY2 are simultaneously generated by the word line selection timing signal φxL.
They are simultaneously brought into a selected state by φX2. Accordingly, operation timing signals φpal and φpa2 of the sense amplifiers SAI and SA2, which are delayed from the word line selection timing signals φX1 and φX2, are also generated simultaneously.

Next, the column address as the initial value is the final address 1 assigned to the left memory array M-ARYI.
023, the data line selection timing signal φy
Only i is set to high level, and the left memory array M-A
RYIO column switch circuit C-5WI is selected and the data line corresponding to the above address is the common complementary data line CDI.
is combined with In response, only the main amplifier operation timing signal φmal is set to high level, the main amplifier MAL is put into the operating state, and the write enable signal WE
In the case of a read operation in which is set to a high level, the stored information from the selected memory cell is sent to the external terminal through the data output circuit of the data input/output circuit I10. Although not shown, the main amplifier MA 1 (MA 2
), a launch circuit is built in, and the common data line CD is activated by the high level of the timing signal φmal.
It is desirable to hold the signal of I (CD2) and send this held signal to the data input/output circuit I10. This makes it possible to shift to the next column switching operation by utilizing the period during which the readout signal is sent to the external terminal after the above-mentioned signal has been taken in. Thereby, high-speed column switching operation can be realized.

Thereafter, when a high-level clock signal is supplied to the external clock signal CL, a corresponding clock signal φ is generated. The address counter circuit C0UNT receives the clock signal φ and performs a +1 walk operation. In this case,
The column system counter circuit (Y) forms the carry signal ca by the above-mentioned footpath operation, and changes the address of itself to 0 and changes the row system address to 5.

Due to the change in the row address mentioned above, the memory array M
-ARYI word line selection operation and sense amplifier SAI
The operation of is once reset by the low level of the timing signals φxi and φpal. Thereafter, the timing signals φx1 and φpal are again at a high level, and the word line selection operation and the sense amplifier SAI operation are performed according to the incremented address 5. In parallel with this, the right memory array M-ARY2, in which the word line has already been selected and the sense amplifier SA2 has been activated, has the data line selection signal ψy2 set to high level. The column switch circuit C-5W2 corresponding to the incremented address 0 is selected, and the data line corresponding to the address is coupled to the common complementary data line CD2. In response, only the main amplifier operation timing signal φma2 is set to high level, and the main amplifier M
A2 is activated. As a result, the data output circuit of the data input/output circuit I10 transmits the stored information from the selected memory cell to the external terminal. below,
Similarly, in synchronization with the C clock signal CL, a read operation of a total of 1024 bits up to column address 1023 is serially performed for row address 4 of right side 1.

For the above row address 4, column address 1023
When reading is completed, the column counter circuit (
The carry signal ca of Y) is generated in the same manner as above, and it is set to address 0 and the row address is set to 6.
change to

Due to the change in the row address mentioned above, the memory array M
-ARY2 word line selection operation and sense amplifier SA2
The operation of is once reset by the low level of the timing signals φX2 and φpa2. Thereafter, the word line selection operation and the operation of the sense amplifier SA2 according to the incremented address 6 are performed again by the high level of the timing signal φ2 and φpa2. In parallel with this, the memory array M-ARYl side whose word line has already been selected is activated by the high level of the data line selection signal φy1, so that the memory array M-ARY1 on the left side corresponding to the incremented address 0 is -ARY1 column switch circuit C-5WI is selected and the data line corresponding to the above address is coupled to the common complementary data line CDI. In response, only the main amplifier operation timing signal φmal is set to a high level, and the main amplifier MAL is put into an operating state. As a result, the data output circuit of the data input/output circuit I10 transmits the stored information from the selected memory cell to the external terminal. Thereafter, in the same manner, in synchronization with the clock signal CL, a total of 1024 bits are read out in serial for row address 5 on the left side up to column address 1023.

The above operations are continuously performed until the chip non-selection state in which the chip selection signal C8 is set to high level. This allows repeated serial reading of all bits if necessary. This type of extended serial access mode uses an address signal formed by a built-in address counter circuit, and takes into account the skinny of the address signal like the static column mode, which supplies address signals from external terminals. Since it is not necessary, the cardiac high-speed readout operation can be performed. In addition, by switching the next word line of one memory array while switching columns of one memory array, continuous reading of all bits can be performed.

Note that access in units of 1 bit is performed using the clock signal C.
This is performed with L set to high level. In this case, the multiplexer circuits included in address buffers R and C-ADB are left on the external address signal side,
Either the left or right memory array M-ARY is brought into a selected state according to an address signal supplied from an external terminal, and a write/read operation is performed in units of one bit.

〔effect〕

(1) By switching the row address and column address using the address signal generated by the built-in address counter circuit, it is possible to perform continuous access to memory cells at high speed without considering address skinny. Effects can be obtained.

(2) During column switching for one of the two memory arrays, by alternately performing the word line selection operation to be accessed next in the other memory array and switching the sense amplifier operation, all bits are The effect is that high-speed access can be performed.

(3) In the extended serial access mode, the built-in address counter circuit forms the address (No. 6), so only the external pins need to be changed, making it extremely easy for the user to handle. Effects can be obtained.

(4) By combining external control signals, 1. l bifu I・
It is possible to selectively perform 2M-class access operations, including access in units of 1 and extended serial access mode (substantially including conventional column static mode and nibble mode). This makes it possible to realize multi-functionality.

(5) By taking in the address signal supplied from the external terminal as an initial value, it is possible to achieve the effect that continuous high-speed reading can be performed from any address.

(6) Due to (1) to 5) above, it is necessary to repeatedly read out a large amount of pixel data at high speed in order to draw high-definition images using a display device such as a CRT. The effect is that a semiconductor memory device suitable for graphical memory can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, when accessing in units of 1 bit, an address signal change detection circuit is built-in to generate the timing signal necessary for internal circuit operation according to the switching of the address signal with the chip selection signal set to low level. Alternatively, the timing signal may be of an internal synchronization type, thereby forming the series of timing signals. Further, the address signal supplied from the external terminal may be supplied in time series from a common external terminal in synchronization with the row address strobe signal RAS and the column address strobe signal CAS.

In addition, the memory array is constructed by dividing each memory mat into multiple memory mats in order to shorten the data line length and word line length to reduce stray capacitance and speed up operation. Good too.

Furthermore, the reference voltage for the read operation of the memory cell may be one that uses a dummy cell or one that precharges the complementary data line to Vcc/2 of the power supply voltage Vcc and uses this precharge voltage as the reference voltage. Furthermore, the specific circuits of the address buffer, its multiplexer circuit, and address counter circuit can take various embodiments. Note that other auxiliary circuits such as an automatic refresh circuit may also be included.

[Application field]

In the above explanation, the present invention was mainly applied to a dynamic type RAM, which is the background of the present invention, but the present invention is not limited to this; it can also be applied to, for example, a static type RAM. .

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the address buffer 1 and address counter circuit. FIG. 3 is a timing chart showing an example of its operation. M-ARYl, M-ARY2...Memory array, SAI
, SA2...Sense amplifier, R-ADB...Row address buffer, C-3W1. C-3W2... Column switch, R, C-ADB... Address buffer, R-DCR
l, R-DCR2...Row decoder, C-DCR...Column decoder, MAI, MA2...Main amplifier, TO
・・Internal control signal generation circuit, Ilo・・Input/output circuit, C
0UNT... Address counter circuit, Figure 1 AX, AY D OE
c, s l/E CLxm xt
x.

Claims (1)

[Claims] 1. Take in the first and second memory arrays divided into two and the address signal supplied from the external terminal as an initial value according to the operation mode signal specified by a predetermined external control signal, and and a multiplexer for transmitting an address signal formed by the address counter circuit to an address decoder according to the operation mode signal; When the selection of the final address in one memory array during column selection is completed, the column selection operation for the other memory array is performed, and the word line selection operation for the next address is performed for the one memory array. A semiconductor memory device characterized by: 2. The first and second memory arrays are configured by dynamic memory cells arranged in a matrix, and the multiplexer is provided at the output section of the address buffer. The semiconductor memory device according to item 1. 3. The first and second memory arrays, when taking in the address signal as an initial value, both perform a word line selection operation in accordance with the address signal. Or the semiconductor memory device according to item 2.