JPH087568A - Dynamic ram - Google Patents

Abstract

PURPOSE:To attain the high speed operation by speeding up a row selecting speed. CONSTITUTION:A row address generating circuit 6 for outputting the internally generated address signal IGAD 1 for address specification updated successively in a prescribed order synchronously with a loc signal CLK with the specified address of row address signal ADr 1 from an outside as a start point is provided in this RAM. An address buffer circuit 2 is used as a circuit for supplying the internally generated address signal IGAD 1 to a row decoder 4 as an internal row address signal IAD 1 at the time of a prescribed mode. Thus, since consecutive selections of plural rows are made possible by fetching a row address signal from the outside once, the row selecting speed is speeded up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM, and more particularly to a dynamic RA having a high speed access mode.
Regarding M.

[0002]

2. Description of the Related Art Dynamic RA requiring high-speed operation
Most of the Ms have high-speed access modes such as page mode, nibble mode, static column mode, and serial mode. In these high-speed access modes, under the same row address, only column addresses are sequentially switched to sequentially read (or write) data existing in a plurality of sense amplifiers to obtain high-speed operation. Is.

This type of conventional general dynamic RA
FIG. 7 shows an example (first example) of M.

This dynamic RAM is composed of a plurality of memory cells (M1) arranged in a matrix in the row and column directions.
1, M12, ..., M21, M22 ,.
22, ...), these plural memory cells (M1
1 to M22, ...) and a plurality of word lines (WL1, WL2, ...) And memory cells (M11. M22 ,. …)
A memory cell array 1x including a chip activation signal C
In response to the activation level (low level) of Eb, the external row address signal ADr is taken in and the internal row address signal IA is taken in.
An address buffer circuit 2x that outputs D and a plurality of word lines (WL1, W1) according to the internal row address signal IAD.
Row decoder 4x having one of L2, ...) as a selection level, and data lines (DL1, DL2, ...) Amplifying data read to bit lines (BL1, BL2 ,.
...), and these data lines (DL1, DL2, ...)
Data for writing the corresponding bit lines (BL1, BL
2, ..., Sense amplifiers (SA1, SA2,
…) And the composition which has. The column selection circuit is omitted in FIG.

Next, the operation of the dynamic RAM will be described with reference to the operation timing chart shown in FIG.

In response to the activation level of the chip activation signal CEb (b indicates that the low level is the activation level. The same applies hereinafter), the address buffer circuit 2x takes in the row address signal ADr from the outside, This is supplied to the row decoder 4x as the internal row address signal IAD. The row decoder 4x decodes the internal row address signal IAD and sets one (eg, WL1) of the plurality of word lines (WL1, WL2, ...) To the selection level. Then, the memory cells (M11, M12, ...) Connected to the word line (WL1) of this selection level are in the selected state, and the data stored in these memory cells are the bit lines (BL1, BL2, ...).
...) is read. Then, these data are amplified by the sense amplifiers (SA1, SA2, ...) And the data lines (D
L1, DL2, ...) and is output to the outside. At this time, in the normal mode, the bit lines (BL1, BL2,
...), one of the data read out is selected by the column selection circuit and output to the outside. In the high-speed access mode, a predetermined number of data read out to the bit lines (BL1, BL2, ...) It is sequentially selected by a column selection circuit or the like and continuously output to the outside.

When the memory cell of the next row (corresponding to word line WL2) is selected and the stored data is read out, the chip activation signal CEb is reset to the inactive level and set to the active level again, and the same operation is performed. Repeat.

When the memory capacity of the dynamic RAM increases, the number of memory cells connected to one bit line increases and the length of the bit line also increases, making it difficult to operate at high speed and increasing power consumption. Therefore, a method of dividing the bit line and the memory cell array and operating the division has been adopted (for example, published by Science Forum, UL.
See SI DRAM technology, pages 89-91).

When the memory capacity further increases (for example, 25
6M bits), and a division operation method by word line division is also adopted.

FIG. 9 shows an example (second example) of a dynamic RAM adopting the word line division operation method.

This dynamic RAM comprises a plurality of memory cells (M1) arranged in a matrix in the row and column directions.
11, M112, ..., M121, M122, ..., M21
1, M212, ..., M221, M222 ,.
11 to M222, ...), and a plurality of sub-words which are provided corresponding to the respective rows of the plurality of memory cells (M111 to 222, ...), and select the memory cells of the corresponding row at the selection level. Line (SWL11, S
WL12, SWL21, SWL22, ..., SWL1
1 to SWL22, ...), and a plurality of mains provided corresponding to a predetermined number (two in this example) of the plurality of sub word lines (SWL11 to SWL22 ,. The word line (MWL1, MWL2, ...) And the read data of the memory cell in the selected state of the corresponding column provided corresponding to each column of the plurality of memory cells and the data for writing to this memory cell are transmitted. The memory cell array 1 having a plurality of bit lines (BL1, BL2, ...) Performed, and the first row address signal ADr1 of the row address signals from the outside are used as the chip activation signal CEb.
In response to the activation level of the first internal row address signal IAD1 and a first address buffer circuit 2a which outputs the first internal row address signal IAD1 and a plurality of main word lines (MWL1, MWL2
Row decoder 4 having one of the selected levels as a selection level,
A second address buffer circuit 3 which takes in a second row address signal ADr2 of the row address signals from the outside in response to the activation level of the chip activation signal CEb and outputs it as a second internal row address signal IAD2. , A plurality of main word lines (MWL1, MWL2, ...) A plurality of sub word lines (SWL11-SWL22, ...)
Of the sub word line selection signals SWS1 and SWS2 for setting one of them as a selection level according to the second internal row address signal IAD2, and a plurality of main word lines. (MW
L1, MWL2, ...) Corresponding sub-word lines provided corresponding to each of the plurality of sub-word lines (SWL11 ... SWL22, ...) And receiving the selection level of the corresponding main word line and the selection level of the corresponding sub-word line. A plurality of word driver circuits (W
D11, WD12, WD21, WD22, ...) and the data read to the bit lines (BL1, BL2, ...) Are amplified and transmitted to the corresponding data lines (DL1, DL2 ,. , DL2, ...), and sense amplifiers (SA1, SA2, ...) For transmitting the write data to the corresponding bit lines (BL1, BL2, ...). The column selection circuit is omitted in FIG. 9 as well.

In this example, a plurality of sub word lines (SWL) are associated with one main word line (eg, MWL1).
11, SWL12) are provided, and the memory cells (M111, M112, ..., M12) are connected to the plurality of sub-word lines.
, M122, ...) are connected, even if the memory capacity increases, the number of memory cells connected to one sub-word line can be suppressed, and high-speed operation can be ensured.

In this example, the first row address signal ADr
1, one (for example, MWL1) of a plurality of main word lines (MWL1, MWL2, ...) Becomes a selection level by the internal row address signal IAD1, and a plurality of lines corresponding to the main word line (MWL1) of this selection level One of the sub word lines (SWL11, SWL12) (for example, SWL11) is the second row address signal ADr.
2. The internal row address signal IAD2 brings the selected level. Then, the sub word line (SWL
11) a plurality of memory cells (M111, M11) connected to
2, ...) are in the selected state, and reading and writing of data with respect to these memory cells are performed similarly to the first example shown in FIG.

Also in this example, when the memory cells (M211, M212, ...) Of the next row (for example, the memory cell row connected to the sub word line SWL21) are brought into the selected state, as shown in the operation timing chart of FIG. It is necessary to reset the chip activation signal CEb to the non-selection level to set it to the activation level again and repeat the same operation.

In these examples, the row address strobe signal RASb is used although the row address signals ADr, ADr1, ADr2 are externally fetched into the address buffer circuits 2a, 2x, 3 by the chip activation signal CEb. Often used.

[0016]

These conventional dynamic RAMs are connected to the same word line (subword line) by a plurality of high speed access modes such as page mode, nibble mode, static column mode and serial mode (in the same row). The data in the memory cells can be read continuously, but when the word line (subword line), that is, the row is switched, the chip activation signal (CE
After resetting b) to the inactive level, this is again set to the active level and the row address signal from the outside is taken in. Therefore, in the memory cells connected to the same bit line (in the same column) Whether or not there is a word line (sub word line),
Whenever the row changes, it is necessary to fetch the row address signal from the outside by the chip activation signal, so that there is a problem that the operation speed becomes slower.

An object of the present invention is to provide a dynamic RAM capable of increasing the row selection speed and achieving a high speed operation.

[0018]

Dynamic R of the present invention
AM is a plurality of memory cells arranged in a matrix in the row direction and the column direction, and a plurality of memory cells provided corresponding to the respective rows of the plurality of memory cells and for selecting the memory cells in the corresponding row at the selection level. One sub-word line, a plurality of main word lines provided corresponding to a predetermined number of these sub-word lines at a ratio of one, and each column of the plurality of memory cells. And a memory cell array having a plurality of bit lines for transmitting read data of the memory cell in the selected state of the corresponding column and write data to the memory cell, and the plurality of main words according to the internal row address signal. A row selection circuit having a selection level of one of the lines and one of a plurality of sub-word lines corresponding to the main word line;
In a predetermined mode, a row address for outputting an internally generated address signal for addressing, which is sequentially updated in a predetermined order from a designated address of the row address signal as a starting point during one operation cycle period corresponding to one row address signal from the outside. And an address buffer circuit that outputs the internal row address signal corresponding to an external row address signal in the normal mode and outputs the internally generated address signal as the internal row address signal in the predetermined mode. There is.

The row selection circuit has a row decoder that sets one of a plurality of main word lines to a selection level according to a first internal row address signal of the internal row address signal, and the internal row address signal. A main word line of the selection level in accordance with a second internal row address signal, and a subword line selection unit having one of a plurality of subword lines corresponding to the selection level as a selection level. However, in the normal mode, the first internal row address signal corresponding to the first row address signal of the external row address signals is output, and in the predetermined mode, the internally generated address signal is output as the first internal row address signal. A first address buffer circuit that outputs a second row address signal corresponding to a second row address signal of the row address signals from the outside. And a second address buffer circuit for outputting the internal row address signal of the first row address signal, and the row address generator is sequentially updated in a predetermined order from the designated address of the first row address signal from the outside. Or the address buffer circuit outputs a first internal row address signal corresponding to the first row address signal of the row address signals from the outside. The first address buffer circuit outputs a second internal row address signal corresponding to a second row address signal of the row address signals from the outside in the normal mode, and outputs an internally generated address signal in the predetermined mode. And a second address buffer circuit for outputting as an internal row address signal of 2. A circuit for outputting the internally generated address signal for addressing, which is sequentially updated in a predetermined order from a designated address of the second row address signal of the address signals, or a first address buffer circuit In the mode, a circuit for outputting the first internally generated address signal as the first internally row address signal is used, and in the predetermined mode, the second internally generated address signal is used as the second internally row address signal. A circuit for outputting, and a row address generation unit, wherein the first and second address designations are sequentially updated in a predetermined order starting from respective designated addresses of the first and second row address signals of an external row address signal. 2 is configured as a circuit for outputting the internally generated address signal, and the sub word line selection section is configured to output a plurality of main word lines. A sub-word line selection circuit that outputs one of the sub-word line selection signals for setting one of the sub-word lines to the selection level in accordance with the second internal row address signal, and a plurality of main word lines A word driver circuit which is provided corresponding to each of the plurality of sub-word lines and receives the selection level of the corresponding main word line and the selection level of the corresponding sub-word line and sets the corresponding sub-word line as the selection level. Composed of.

Further, the memory cell array is provided with a plurality of memory cells arranged in a matrix in the row direction and the column direction, and a memory of a corresponding row provided at a selection level corresponding to each row of the plurality of memory cells. A plurality of word lines which bring the cells into a selected state, and read data of the memory cells in the selected state of the corresponding column provided corresponding to each column of the plurality of memory cells and data for writing to the memory cells. A circuit having a plurality of bit lines for transmission is provided, and the row selection circuit is configured as a circuit that sets one of the plurality of word lines to a selection level according to an internal row address signal.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional dynamic RAM shown in FIG. 9 in that the internal row address signal MAD corresponding to the external first row address signal ADr1 is used.
In response to 1, the designated address of the internal row address signal MAD1 is used as a starting point and the address designation is sequentially updated (eg, sequentially counted up) in a prescribed order in synchronization with a prescribed clock signal CLK (eg, system clock signal). A row address generation circuit 6 for outputting an internally generated address signal IGAD1 is provided, and the first address buffer circuit 2 is
External first row address signal AD in normal mode
A circuit which outputs the first internal row address signal IAD1 corresponding to r1 and outputs the internally generated address signal IGAD1 as the first internal row address signal IAD1 in the predetermined mode (for example, the high-speed row access mode) and supplies it to the row decoder 4. There is a point.

Next, the operation of this embodiment in the predetermined mode will be described with reference to the operation timing chart shown in FIG.

The address buffer circuit 2 takes in the row address signal ADr1 from the outside in response to the activation level of the chip activation signal CEb, and outputs the internal row address signal MAD.
It is supplied to the row address generation circuit 6 as 1.

The row address generation circuit 6 has a clock signal C.
Internal row address signal MAD supplied in synchronization with LK
An internally generated address signal IGAD1 for addressing which sequentially increments from a designated address of 1 (the same as the designated address of the row address signal ADr1) is output and supplied to the address buffer circuit 2. Then, the address buffer circuit 2 supplies the internally generated address signal IGAD1 to the row decoder 4 as the internal row address signal IAD1.

The row decoder 4 decodes the supplied internal row address signal IAD1 to obtain 1 of the clock signal CLK.
For example, the main word line MWL1 is sequentially set to the selection level in the second generation, and the main word line MWL2 is sequentially set to the selection level in the second generation, and the selection level is supplied to the corresponding word driver circuit.

On the other hand, the address buffer circuit 3 takes in the second row address signal ADr2 from the outside in response to the activation level of the chip activation signal CEb and supplies it to the sub word line selection circuit 5 as an internal row address signal IAD2. To do. The sub word line selection circuit 5 decodes the supplied internal row address signal IAD2, and outputs the sub word line selection signal S
The word driver circuit (WD11, WD1) with one of WS1 and SWS2 (for example, SWS1) as a selection level
2, WD21, WD22, ...).

Word driver circuit (WD11, WD1
2, WD21, WD22, ...) When the signals of the main word line and the sub-word line selection signal supplied simultaneously become the selection level, the corresponding sub-word line is set to the selection level. Therefore, in the above example, the sub word line SWL11 becomes the selection level at the first generation of the clock signal CLK,
In the second generation, the sub word line SWL21 becomes the selection level.

In this way, when data is read from or written in a plurality of memory cells connected to the same bit line, the row address signal from the outside needs to be fetched only once to determine the starting point, and the succeeding rows are fetched. Since the address is automatically generated by the row address generation circuit 6, the chip activation signal CEb is changed to a deactivation level or activation level each time the row address changes, which is significantly larger than that of the conventional example in which a row address signal from the outside is taken in. The operating speed can be increased.

FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG. 4 is an operation timing chart of this embodiment.

In the above-described first embodiment, an example in which the row address generating circuit 6 is provided and a plurality of main word lines are successively and continuously set to the selection level by once receiving the row address signal from the outside is shown. However, in the second embodiment,
An example is shown in which a row address generation circuit 6a is provided, and a plurality of sub-word lines corresponding to one main word line are successively and continuously set to a selection level by once receiving a row address signal from the outside. .

This embodiment is different from the conventional dynamic RAM shown in FIG. 9 in that it receives an external second row address signal ADr2 and a corresponding internal row address signal MAD2, and outputs the internal row address signal MAD2. Row address generation for outputting an internal address signal IGAD2 for designating an address (two addresses in this embodiment because two subword lines can be selected) is sequentially updated in a predetermined order starting from the designated address in synchronization with the clock signal CLK. The circuit 6a is provided to output the second row address buffer circuit 3a to the second internal row address signal IAD2 corresponding to the second row address signal ADr2 from the outside in the normal mode and to output the internally generated address IGAD2 in the predetermined mode. A circuit for outputting as the second internal row address signal IAD2 and supplying it to the sub-word line selection circuit 5. There in the points.

The operation of this embodiment will be described below.

Address buffer circuit 3a fetches external row address signal ADr2 in response to the activation level of chip activation signal CEb, and internal row address signal MA.
It is supplied to the row address generation circuit 6a as D2.

The row address generation circuit 6a synchronizes with the clock signal CLK and supplies the supplied internal row address signal MA.
An internally generated address signal IGAD2 for designating an address (only two addresses) that is sequentially updated (for example, counting up) starting from a designated address of D2 (the same as the designated address of the row address signal ADr2) is supplied to the address buffer circuit 3a. . And the address buffer circuit 3a
Supplies the internally generated address signal IGAD2 to the sub word line selection circuit 5 as an internal row address signal IAD2.

The sub-word line selection circuit 5 decodes the supplied internal row address signal IAD2 and sequentially sets one of the sub-word line selection signals SWS1 and SWS2 to the selection level according to the designated address of the internal row address signal IAD2. Word driver circuit (WD11, WD1
2, WD21, WD22, ...).

On the other hand, the address buffer circuit 2a takes in the first row address signal ADr1 from the outside in response to the activation level of the chip activation signal CEb and supplies it to the row decoder 4 as an internal row address signal IAD1. The row decoder 4 decodes the supplied internal row address signal IAD1 to generate a plurality of main word lines (MWL1, MW).
One of L2, ... (MWL1) is set as the selection level. Therefore, in the above example, the sub word line SWL11 becomes the selection level at the first generation of the clock signal CLK,
The second word sets the sub word line SWL12 to the selection level.

Also in this embodiment, the same effect as that of the first embodiment can be obtained.

FIG. 5 is a block diagram showing a third embodiment of the present invention, and FIG. 6 is an operation timing chart of this embodiment.

This third embodiment is based on the above-mentioned first and second embodiments.
The first embodiment is integrated into one, and the configuration and the operation thereof are basically the same as those of the first and second embodiments, and thus the description thereof will be omitted. However, in the first and second embodiments, only one of the main word line and the sub word line is automatically selected continuously, whereas in the third embodiment, both the main word line and the sub lead line are automatically selected. Since automatic continuous selection is possible, there is an advantage that the applicable range is expanded.

Although the word lines are divided into the main word lines and the sub word lines in these embodiments, the word lines are not divided in this way, for example, as shown in FIG. The present invention can be applied even to such a dynamic RAM.

[0043]

As described above, according to the present invention, a row address for generating an internal row address signal (internally generated address signal) that is sequentially updated starting from a designated address of a row address signal fetched from the outside. Since a signal generation circuit is provided and a plurality of word lines, that is, a plurality of memory cell rows of the memory cell array are sequentially and sequentially selected by the internal row address signal, one row address signal from the outside is generated. Since multiple rows of memory cells can be selected consecutively by taking in, the row selection speed can be greatly increased compared to the conventional example in which row address signals from the outside are taken in each time the row designation changes, and therefore high-speed operation is possible. Is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is an operation timing chart of the embodiment shown in FIG.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

6 is an operation timing chart of the embodiment shown in FIG.

FIG. 7 is a block diagram showing a first example of a conventional dynamic RAM.

8 is an operation timing chart of the dynamic RAM shown in FIG.

FIG. 9 is a block diagram showing a second example of a conventional dynamic RAM.

10 is an operation timing chart of the dynamic RAM shown in FIG.

[Explanation of symbols]

 1, 1x Memory cell array 2, 2a, 2x, 3, 3a Address buffer circuit 4, 4x Row decoder 5 Sub word line selection circuit 6, 6a, 6b Row address generation circuit BL1, BL2 Bit line DL1, DL2 Data line M11-22, M111 to M222 memory cells MWL1 and MWL2 main word lines SA1 and SA2 sense amplifiers SWL11 to SWL22 sub word lines WD11 to WD22 word driver circuits WL1 and WL2 word lines

Claims (6)

[Claims] 1. A plurality of memory cells arranged in a matrix in a row direction and a column direction, and memory cells of a corresponding row provided in correspondence with each row of the plurality of memory cells are set to a selected state. A plurality of sub-word lines, a plurality of main word lines provided corresponding to a predetermined number of each of the plurality of sub-word lines at a rate of one,
And a plurality of bit lines provided corresponding to the respective columns of the plurality of memory cells, for transmitting read data of the memory cells in the selected state of the corresponding columns and transmission of data for writing to the memory cells. A memory cell array, a row selection circuit for setting one of the plurality of main word lines and one of a plurality of sub word lines corresponding to the main word line to a selection level according to an internal row address signal, In the mode, a row address generation that outputs an internally generated address signal for addressing which is sequentially updated in a predetermined order from a designated address of this row address signal as a starting point during one operation cycle period corresponding to one row address signal from the outside And the internal row address signal corresponding to the row address signal from the outside in the normal mode Dynamic RAM, characterized in that it comprises an address buffer circuit for outputting the internal generation address signal as the internal row address signal to. 2. A row selection circuit, wherein a row decoder sets one of a plurality of main word lines to a selection level according to a first internal row address signal of the internal row address signal, and the internal row address signal. A main word line of the selection level in accordance with a second internal row address signal, and a subword line selection unit having one of a plurality of subword lines corresponding to the selection level as a selection level. However, in the normal mode, the first internal row address signal corresponding to the first row address signal of the external row address signals is output, and in the predetermined mode, the internally generated address signal is output as the first internal row address signal. And a second address buffer circuit corresponding to a second row address signal of the row address signals from the outside. Second output of department address signal
And an address buffer circuit for addressing the internally generated address signal for addressing, which is sequentially updated in a predetermined order from a designated address of the first row address signal from the outside as a starting point. The dynamic RAM according to claim 1, wherein the dynamic RAM is an output circuit. 3. A first address buffer circuit that outputs a first internal row address signal corresponding to a first row address signal of the row address signals from the outside, and an external address buffer circuit in the normal mode. A second row address signal corresponding to a second row address signal of the row address signals from
And a second address buffer circuit for outputting an internally generated address signal as the second internal row address signal in a predetermined mode, and a row address generator from the outside. 3. A dynamic RAM according to claim 2, wherein the internally generated address signal for addressing is sequentially updated in a predetermined order from a designated address of a second row address signal among the row address signals as a starting point. 4. The first address buffer circuit is a circuit for outputting the first internally generated address signal as a first internal row address signal in a predetermined mode, and the second address buffer circuit is a second circuit in the predetermined mode. Of the internally generated address signal is output as a second internal row address signal, and the row address generation unit is configured to output a predetermined address from each of designated addresses of the first and second row address signals of the row address signal from the outside. 3. The dynamic RAM according to claim 2, wherein the circuit outputs the first and second internally generated address signals for addressing which are sequentially updated in order. 5. A sub word line selection unit sets one of sub word line selection signals for setting one of a plurality of sub word lines of each of a plurality of main word lines to a second internal row address. A subword line selection circuit that outputs a selection level according to a signal, and a selection level of a subword line corresponding to the selection level of the corresponding main word line provided corresponding to each of the plurality of subword lines of each of the plurality of main word lines 3. The dynamic RAM according to claim 2, further comprising a word driver circuit which receives a signal and sets a corresponding sub word line to a selection level. 6. A memory cell array having a plurality of memory cells arranged in a matrix in a row direction and a column direction, and a memory of a row corresponding to each row of the plurality of memory cells at a selection level. A plurality of word lines which bring the cells into a selected state, and read data of the memory cells in the selected state of the corresponding column provided corresponding to each column of the plurality of memory cells and data for writing to the memory cells. 2. A dynamic circuit according to claim 1, wherein the row selection circuit is a circuit having a plurality of bit lines for transmission, and the row selection circuit is a circuit which sets one of the plurality of word lines to a selection level according to an internal row address signal. RAM.