JPS5668990A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS5668990A
JPS5668990A JP14469479A JP14469479A JPS5668990A JP S5668990 A JPS5668990 A JP S5668990A JP 14469479 A JP14469479 A JP 14469479A JP 14469479 A JP14469479 A JP 14469479A JP S5668990 A JPS5668990 A JP S5668990A
Authority
JP
Japan
Prior art keywords
circuit
address
internal
signal
internal clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14469479A
Other languages
Japanese (ja)
Other versions
JPS6220632B2 (en
Inventor
Yasuo Akatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14469479A priority Critical patent/JPS5668990A/en
Priority to US06/139,595 priority patent/US4337525A/en
Priority to EP80102068A priority patent/EP0017990B1/en
Priority to DE8080102068T priority patent/DE3070410D1/en
Publication of JPS5668990A publication Critical patent/JPS5668990A/en
Publication of JPS6220632B2 publication Critical patent/JPS6220632B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To obtain a memory which has no problem of the address setup time, by taking the external write signal into the inside with synchronization via the internal clock generated through the logic change of the address input in an internal synchronous memory. CONSTITUTION:The internal clock generating circuit G detects the logic change of the address inputs A0-An through the delay circuit and the exclusive OR circuit and then generates the internal clock CE. The control signal generating circuit G1 receives the clock CE and then generates successively and with a delay the control signals CE1-CE4 to control the address buffer circuit B, address decoder circuit DE, memory cell array C and input/output buffer circuit IO each. In this case, the internal write signal W delivers the reverse-phase signal of the external write signal through the AND circuit A with the synchronization secured by the control signal CE2 of the address decoder circuit DE.
JP14469479A 1979-04-17 1979-11-08 Memory circuit Granted JPS5668990A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP14469479A JPS5668990A (en) 1979-11-08 1979-11-08 Memory circuit
US06/139,595 US4337525A (en) 1979-04-17 1980-04-11 Asynchronous circuit responsive to changes in logic level
EP80102068A EP0017990B1 (en) 1979-04-17 1980-04-17 Integrated memory circuit
DE8080102068T DE3070410D1 (en) 1979-04-17 1980-04-17 Integrated memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14469479A JPS5668990A (en) 1979-11-08 1979-11-08 Memory circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP63031126A Division JPH01138673A (en) 1988-02-13 1988-02-13 Memory circuit

Publications (2)

Publication Number Publication Date
JPS5668990A true JPS5668990A (en) 1981-06-09
JPS6220632B2 JPS6220632B2 (en) 1987-05-08

Family

ID=15368090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14469479A Granted JPS5668990A (en) 1979-04-17 1979-11-08 Memory circuit

Country Status (1)

Country Link
JP (1) JPS5668990A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835783A (en) * 1981-08-24 1983-03-02 Fujitsu Ltd Write control system for semiconductor memory
JPS58169383A (en) * 1982-03-30 1983-10-05 Fujitsu Ltd Semiconductor storage device
JPS60555A (en) * 1982-11-15 1985-01-05 デ−タ−・ゼネラル・コ−ポレ−シヨン General-purpose memory
JPS60179993A (en) * 1984-02-27 1985-09-13 Toshiba Corp Random access memory
JPS60182595A (en) * 1984-03-01 1985-09-18 Toshiba Corp Random access memory
JPS60253091A (en) * 1984-05-30 1985-12-13 Fujitsu Ltd Semiconductor storage device
JPS62137796A (en) * 1985-12-10 1987-06-20 Matsushita Electronics Corp Word line driving circuit
JPS62277692A (en) * 1986-05-27 1987-12-02 Fujitsu Ltd Output buffer circuit for semiconductor memory device
JPS6387692A (en) * 1987-03-20 1988-04-18 Toshiba Corp Semiconductor memory
JPS63228489A (en) * 1987-03-17 1988-09-22 Sony Corp Memory device
JPH0369095A (en) * 1981-08-05 1991-03-25 General Instr Corp Memory cell for use in memory logic array with data column of two conductors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152931A (en) * 1978-05-24 1979-12-01 Hitachi Ltd Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152931A (en) * 1978-05-24 1979-12-01 Hitachi Ltd Semiconductor memory device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0369095A (en) * 1981-08-05 1991-03-25 General Instr Corp Memory cell for use in memory logic array with data column of two conductors
JPS5835783A (en) * 1981-08-24 1983-03-02 Fujitsu Ltd Write control system for semiconductor memory
JPS6249676B2 (en) * 1981-08-24 1987-10-20 Fujitsu Ltd
JPS58169383A (en) * 1982-03-30 1983-10-05 Fujitsu Ltd Semiconductor storage device
JPS60555A (en) * 1982-11-15 1985-01-05 デ−タ−・ゼネラル・コ−ポレ−シヨン General-purpose memory
JPS60179993A (en) * 1984-02-27 1985-09-13 Toshiba Corp Random access memory
JPS60182595A (en) * 1984-03-01 1985-09-18 Toshiba Corp Random access memory
JPS60253091A (en) * 1984-05-30 1985-12-13 Fujitsu Ltd Semiconductor storage device
JPH0453036B2 (en) * 1984-05-30 1992-08-25 Fujitsu Ltd
JPS62137796A (en) * 1985-12-10 1987-06-20 Matsushita Electronics Corp Word line driving circuit
JPS62277692A (en) * 1986-05-27 1987-12-02 Fujitsu Ltd Output buffer circuit for semiconductor memory device
JPS63228489A (en) * 1987-03-17 1988-09-22 Sony Corp Memory device
JPH034992B2 (en) * 1987-03-20 1991-01-24 Tokyo Shibaura Electric Co
JPS6387692A (en) * 1987-03-20 1988-04-18 Toshiba Corp Semiconductor memory

Also Published As

Publication number Publication date
JPS6220632B2 (en) 1987-05-08

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