JPS5549073A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5549073A
JPS5549073A JP12243378A JP12243378A JPS5549073A JP S5549073 A JPS5549073 A JP S5549073A JP 12243378 A JP12243378 A JP 12243378A JP 12243378 A JP12243378 A JP 12243378A JP S5549073 A JPS5549073 A JP S5549073A
Authority
JP
Japan
Prior art keywords
memory
synchronizing
input
output
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12243378A
Other languages
Japanese (ja)
Other versions
JPS6123707B2 (en
Inventor
Sohei Takemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP12243378A priority Critical patent/JPS5549073A/en
Publication of JPS5549073A publication Critical patent/JPS5549073A/en
Publication of JPS6123707B2 publication Critical patent/JPS6123707B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE: To make it possible to perform write and read operations synchronously by forming a frame memory of two memory banks and by providing a buffer memory on an input or output circuit side.
CONSTITUTION: A frame memory is formed of memory bank 1 and memory bank 2, writing operation is performed by input controller 6 and buffer memories 11 and 12 synchronizing with an input signal and read operation is also performed by synchronizing clocks obtained lagging input synchronism by latch circuits 13∼ 16, output control circuits 8 and 9 and a P/S circuit as an output buffer. In this case, cycles of reading clocks are specified to more than those twice as many as of write cycles so as to obtain an synchronizing output without miseading. On the other hand, cycle time of memory unit is made less than twice as many as of of a memory element for high-speed processing.
COPYRIGHT: (C)1980,JPO&Japio
JP12243378A 1978-10-04 1978-10-04 Memory unit Granted JPS5549073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12243378A JPS5549073A (en) 1978-10-04 1978-10-04 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12243378A JPS5549073A (en) 1978-10-04 1978-10-04 Memory unit

Publications (2)

Publication Number Publication Date
JPS5549073A true JPS5549073A (en) 1980-04-08
JPS6123707B2 JPS6123707B2 (en) 1986-06-06

Family

ID=14835713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12243378A Granted JPS5549073A (en) 1978-10-04 1978-10-04 Memory unit

Country Status (1)

Country Link
JP (1) JPS5549073A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023835A (en) * 1986-02-19 1991-06-11 Hitachi, Ltd. Semiconductor memory system for use in logic LSI's
US5270981A (en) * 1985-07-30 1993-12-14 Kabushiki Kaisha Toshiba Field memory device functioning as a variable stage shift register with gated feedback from its output to its input
JPH0730435A (en) * 1993-07-14 1995-01-31 Nec Corp Error correcting circuit
US6381191B2 (en) * 1995-07-03 2002-04-30 Mitsubishi Denki Kabushiki Kaisha Fast accessible dynamic type semiconductor memory device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270981A (en) * 1985-07-30 1993-12-14 Kabushiki Kaisha Toshiba Field memory device functioning as a variable stage shift register with gated feedback from its output to its input
US5023835A (en) * 1986-02-19 1991-06-11 Hitachi, Ltd. Semiconductor memory system for use in logic LSI's
JPH0730435A (en) * 1993-07-14 1995-01-31 Nec Corp Error correcting circuit
US6381191B2 (en) * 1995-07-03 2002-04-30 Mitsubishi Denki Kabushiki Kaisha Fast accessible dynamic type semiconductor memory device
US6587392B2 (en) 1995-07-03 2003-07-01 Mitsubishi Denki Kabushiki Kaisha Fast accessible dynamic type semiconductor memory device

Also Published As

Publication number Publication date
JPS6123707B2 (en) 1986-06-06

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