JPS5470735A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS5470735A
JPS5470735A JP13825677A JP13825677A JPS5470735A JP S5470735 A JPS5470735 A JP S5470735A JP 13825677 A JP13825677 A JP 13825677A JP 13825677 A JP13825677 A JP 13825677A JP S5470735 A JPS5470735 A JP S5470735A
Authority
JP
Japan
Prior art keywords
memory
speed
cpu1
low
action
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13825677A
Other languages
Japanese (ja)
Inventor
Tadahiro Yanagisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13825677A priority Critical patent/JPS5470735A/en
Publication of JPS5470735A publication Critical patent/JPS5470735A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the use of the low-speed memory to a synchronous computer by sending the output to CPU from the signal generator and making the CPU action hold to the data bus in case the action time of the memory is detected to be longer than that of CPU via a decoder.
CONSTITUTION: The read/write output terminal of CPU1 is connected to the read/ write input terminal of high-speed and low-speed action memories 20 and 21 each via control bus CB. Decoder 5 detects whether the corresponding memory is memory 21 featuring a longer action time than CPU1 based on the address signal to the memory. In case the memory is detected to be low-speed memory 21, the output is sent to CPU1 from signal generator 7 to make the data bus hold the action of CPU1. As a result, the low-speed memory can be applied to the synchronous computer.
COPYRIGHT: (C)1979,JPO&Japio
JP13825677A 1977-11-17 1977-11-17 Electronic computer Pending JPS5470735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13825677A JPS5470735A (en) 1977-11-17 1977-11-17 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13825677A JPS5470735A (en) 1977-11-17 1977-11-17 Electronic computer

Publications (1)

Publication Number Publication Date
JPS5470735A true JPS5470735A (en) 1979-06-06

Family

ID=15217689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13825677A Pending JPS5470735A (en) 1977-11-17 1977-11-17 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5470735A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694451A (en) * 1979-12-27 1981-07-30 Fujitsu Ltd Microprocessor incorporating memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694451A (en) * 1979-12-27 1981-07-30 Fujitsu Ltd Microprocessor incorporating memory

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