JPS5566023A - Operation processing unit - Google Patents

Operation processing unit

Info

Publication number
JPS5566023A
JPS5566023A JP13927578A JP13927578A JPS5566023A JP S5566023 A JPS5566023 A JP S5566023A JP 13927578 A JP13927578 A JP 13927578A JP 13927578 A JP13927578 A JP 13927578A JP S5566023 A JPS5566023 A JP S5566023A
Authority
JP
Japan
Prior art keywords
signal
cpu1
outputted
inputted
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13927578A
Other languages
Japanese (ja)
Other versions
JPS6153736B2 (en
Inventor
Tsuguji Tateuchi
Shigeru Hirahata
Teruhiro Takezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13927578A priority Critical patent/JPS5566023A/en
Priority to DE2922540A priority patent/DE2922540C2/en
Priority to US06/044,379 priority patent/US4298931A/en
Publication of JPS5566023A publication Critical patent/JPS5566023A/en
Publication of JPS6153736B2 publication Critical patent/JPS6153736B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to access freely two-system RAMs by prolonging the period of a clock signal when a selected storage circuit does not agree with a storage circuit which a CPU accesses.
CONSTITUTION: When RAM switching signal f generated in 21 in clock signal generation circuit 4 is inputted, clock signal a is inputted to CPU1, and least significant address signal j is "1", and therefore, output signal k of three-input AND circuit 24 is not outputted by exclusive OR 23 between f and j. Next, when signal f disappears, k is outputted, and clock signal b is outputted instead of signal a, and first RAM15 is connected to CPU1, thereby enabling read/write. Thus, signal a is prolonged in case that a RAM connected to CPU1 is accessed when signal a is inputted, and signal b is outputted when the RAM to be accessed again and CPU1 are connected after that, so that data can be read or write from the CPU.
COPYRIGHT: (C)1980,JPO&Japio
JP13927578A 1978-06-02 1978-11-11 Operation processing unit Granted JPS5566023A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP13927578A JPS5566023A (en) 1978-11-11 1978-11-11 Operation processing unit
DE2922540A DE2922540C2 (en) 1978-06-02 1979-06-01 Data processing system
US06/044,379 US4298931A (en) 1978-06-02 1979-06-01 Character pattern display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13927578A JPS5566023A (en) 1978-11-11 1978-11-11 Operation processing unit

Publications (2)

Publication Number Publication Date
JPS5566023A true JPS5566023A (en) 1980-05-19
JPS6153736B2 JPS6153736B2 (en) 1986-11-19

Family

ID=15241482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13927578A Granted JPS5566023A (en) 1978-06-02 1978-11-11 Operation processing unit

Country Status (1)

Country Link
JP (1) JPS5566023A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5960477A (en) * 1982-09-30 1984-04-06 富士通株式会社 Bit map memory control system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128440A (en) * 1974-09-03 1976-03-10 Matsushita Electric Ind Co Ltd DEISUPURE ISOCHI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128440A (en) * 1974-09-03 1976-03-10 Matsushita Electric Ind Co Ltd DEISUPURE ISOCHI

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5960477A (en) * 1982-09-30 1984-04-06 富士通株式会社 Bit map memory control system

Also Published As

Publication number Publication date
JPS6153736B2 (en) 1986-11-19

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