JPS60182595A - Random access memory - Google Patents

Abstract

PURPOSE:To prevent erroneous actions of a memory internal circuit at the time of a change in an address signal input by writing a write input signal after it is delayed. CONSTITUTION:As soon as an address signal A changes (time t0), a write input signal WI is inputted and delayed by a delay circuit 27 having a RC time constant. The delay time is set as a time T3 from a time t1 when a precharge control signal PS becomes a low level to a time t2 when the specific period expires. As a result, after the time T3 has expired since the input signal WI became a high level, a control signal WS becomes a high level, and writing is performed. As soon as the signal A changes at a time t3, the signal WI becomes a low level. Then an output of a NAND gate 26 becomes a high level, the signal WS from an invertor 28 drops to a low level at a time t4, and at a time t5 a word line signal (j) is made in the non-selected condition. Finally a word line signal (i) is in the selected condition.

Description

[Detailed Description of the Invention] The present invention relates to a random access memory.
In particular, the present invention relates to improving the characteristics of the memory 1 having a precharge circuit.

[Technical background of the invention]

In recent years, as semiconductor memory devices have become more highly integrated,
There is a demand for higher speed and lower power consumption. In order to meet these demands, static random access memory uses an address transition detector and dynamically operates internal circuits based on its output and signal, thereby increasing speed and reducing power consumption. method has been adopted.

g 1 [Silj: indicates a random access memory that aims to increase the speed by recharging the bit line using the output pulse of the address transition detector. In the figure, an address input circuit having a 111ri address displacement detector,
Address signal A is supplied to address input terminal 11a of address input circuit l1, and its output is supplied to precharge control circuit 12, row decoder 13, and column decoder 14. The output of the precharge control circuit l2 (precharge control signal PS) is applied to the bit lines BLl, f low to
One end of the BLn signal line 5 is supplied to a precharge circuit 15 to which it is connected. The above bit line B Ll *
Word lines WL1 to WL1 to which the output of the row decoder 13 is supplied intersect with B Ll to B Ln t B Ln
W L m are arranged, and bit lines BL1. B mouth~B'
Memory cells M1 . ~Mmn are arranged, respectively. The above bit line BL1゜BLI~BLn-
A write circuit J6 is connected to the other end of BLn, and this write circuit 16 is controlled by a write control signal WS output from a write control circuit 17. A write input signal type is supplied to the terminal 17aK of the write control circuit 17. Then, the write data Din supplied to the data input/output terminal 18 is transferred to the input/output circuit 19. The column decoder 14. Sense amplifier 20 and write circuit 1
It is written into memory cells Mth to Mmn through 6f. Also, memory cell M! The data read from the write circuits 16. Sense amplifier 20. An output signal is output from the data input/output terminal 18 via the column decoder 14 and the input/output circuit 19, respectively. It can be read as nt.

Next, the operation in the above configuration will be clarified. In the case of a read operation, when the address input circuit 11 hair drain signal A is input from the address input terminal 11a, the output of the address input circuit 1 is sent to the row and column decoder 1.
3.14, and a signal indicating that the address has changed is also supplied to the precharge control circuit 12. As a result, the precharge control signal ps is supplied from the precharge control circuit 12 to the precharge circuit 15, and the bit lines BL, BL, to BLn are supplied with the precharge control signal ps.

Then, the address signal A input to the row decoder 13 is decoded, and the word line WL1 is precharged.
~WLm is selected. Now word line WL
, the contents of memory cells Mth to MIn are bit lines BLl, BLI to B Ln r B Ln
is output to. The above bit lines BLl, B port to B Ln
* The signal read out at temperature B is amplified by the sense amplifier 20, and only the data of the column selected by the column decoder 14 is sent to the data input/output terminal 18 via the input/output circuit 19.
Read from.

On the other hand, when writing data, as shown in the timing chart of FIG. 2, when address signal A changes at time to, the output of address input circuit 1 is supplied to row decoder 13 and column decoder 14. At the same time, a signal indicating a change in address signal A is supplied to precharge control circuit 12. Then, the output of this precharge control circuit 12 is supplied to the precharge circuit 15 as a precharge control signal PS (time 1.). Next, at time t2, the word line signal i that was selected before the address input is set to a non-selected state by the signal decoded by the row decoder 13, and the word line signal j corresponding to the address input is further selected. Ru. Write input signal W
I is applied after or simultaneously with the input of the address signal person, and FIG. 2 shows the case where they are applied simultaneously. When the write input signal WI is applied (time to), the write control circuit 17 outputs the write control signal WS at time t3. At this time, in order to prevent data from being erroneously written to the memory cell, the write control signal WS is activated (
)-Irepel) by the write control circuit 17. That is, the time T summer between time tz and t3 is made to be 0<T+J. Also, at the same time as the next change in address signal A (time ts), write input signal Wl is inactive (low level). In order to prevent erroneous data writing even when
, r Q <Tz J 'c.

[Problems with background technology]

However, in a random access memory equipped with a precharge circuit as shown in FIG.
Despite satisfying the conditions (0<TI, 0<T2) that no erroneous data writing to the memory cell occurs between Tw may overlap (between times t3 and t4 in FIG. 2). In such a case, in the column selected by the column decoder 14, a current path of power supply→precharge circuit→bit line→write circuit→ground point is formed, and a large DC current flows. below,
This direct current will be explained in detail. Now, focusing on one selected bit line (BLI, port B), the circuit configuration of FIG. 1 is concretely illustrated as shown in FIG. 3.

One end of bit line BL1 t B LH and power supply voltage vDD
MOS transistors Ql *Qz whose conduction is controlled by a precharge control signal PS are inserted between the terminals 211 * 212 to which the voltage is applied. These ms transistors QtyQz constitute the precharge circuit 15 and are provided for each bit line. The bit line BL1. The word line W Ll intersects with BL.
, WL2 *... are arranged, and these word lines W
L1 r WL2 g... and bit line BLI s B
Note 1 texel M11 # M2 at each intersection with LI
1 @... is placed. In addition, the bit line B L
A sense amplifier 7'2o is connected between bit lines BL1, B, and Ll, and M is connected to the other end of the bit line BL1, B, and Ll.
One end of OS I-transistor Q3*Q4 is connected. The other ends of the MOS transistors Q31Q4 are connected in common, and a ground point is connected to this common connection point via a MOS transistor Q5 whose conduction is controlled by the output of the NAND dart as the column decoder 14. MO8 above)
The conduction of the transistor Q4 is controlled by a signal obtained by inverting the output of the Nant gate 22, which is supplied with the input signal D1n and the write control signal WS, by the inverter 23.
The OS transistor Q3 is connected to the Nands gate 2 to which the output of the Nands dart 22 and the write control signal section are supplied.
The conduction is controlled by a signal obtained by inverting the output of No. 4 by an inverter 25.

In the above configuration, between times t3 and t4 in the timing chart of FIG. 2, the f IJ Charo control signal PS is at a high (,'') ('') level, so the MO3I transistor Qt IQz is in the on state. be. In addition, since the write 1 write control signal WS is at the "H# level," the inverter 2
2. Either output of 24 is "H" level.
8) One of transistors Q3-Q4 is turned on. At this time, bit line BL1mBL1 is selected, so
MOS transistor Q5 is in an on state. Therefore, from terminals 211.212 to MOS) transistor QllQ2
, bit line BL1. B port, MOS1-ransistor Q3*
Direct current flows through one of the transistors Q4 and the MOS transistor Q5. This DC current causes a voltage drop and noise in the precharge power supply line, resulting in a bit line voltage drop. If you move on to the next operation in this state, data input/output terminal 1 will be connected to the selected column.
There is no particular problem since the signal applied to the bit line 8 is written to the memory cell, but in the non-selected column, a decrease in the potential of the bit line due to the bit line voltage and noise adversely affects the memory cell and other circuits.

In particular, when a bit line potential launch type sense amplifier is used, erroneous data is latched and the information stored in the memory cell is rewritten with this data, resulting in erroneous writing.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a random access memory that can prevent malfunctions of internal circuits of the memory even if a write input signal is input at the same time as or immediately after a change in address signal input.

[Summary of the invention]

That is, in this invention, in order to achieve the above object, a write control signal for controlling the write circuit is
By delaying the supply until the precharge operation performed in response to a change in the address signal is completed, the time overlap between the precharging operation and the write operation is prevented, and the write operation is started after the precharge operation is completed. That's what I do.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows a specific example of the configuration of the cooling control circuit 17 shown in FIG. 1. In FIG. In other words, one input signal W is input to one input terminal of the NAND dart 26.
I is supplied, and the write input signal WI is supplied to the other input terminal via a delay circuit 27. The output of the NAND dart 26 is inverted by an inverter 28, and the output of the inverter 28 is supplied as a write control signal 2 to the write circuit 16 in FIG.

The operation of the above configuration will be described with reference to the timing chart of FIG. Incidentally, since the basic operation is the same as that shown in FIG. 1, detailed explanation thereof will be omitted. That is, the change in address signal A (time to
), this write input signal WI is delayed by the delay circuit 27. This delay time is determined by the precharge control signal PS
It is set at time t2, which is a predetermined period of time after the time tl when the write input signal WI becomes low (°°L") level. Therefore, 13 hours have elapsed since the write input signal WI became the Ita" level. , the write control signal WS is °゛H”
Writing is performed at the level (time tz). Next, at time t3, when the address signal A changes and the write-in input signal WI goes to the "L" level, the output of the Nando Dart 26 goes to the °'H" level, so the write control signal is output from the inverter 28. WS reaches the ``Ln level'' at time t4. Then, at time t5, the word line signal j becomes a non-selected state, and the word line signal amount becomes a selected state. Therefore, the precharge operation and the write operation do not overlap in time.

FIG. 6 shows a specific example of the configuration of the delay circuit 27 shown in FIG.
The delay time T3 is obtained by the C time constant.

FIG. 7 shows a specific example of the structure of the delay circuit 27 in FIG. 4, and a delay time T3 is obtained by cascading even-numbered stages of inverters "9i + 292, . . . 29n."

As described above, even if the write input signal W is input at the same time as or immediately after the input of the address signal A, the preaching operation is completed and the delay circuit 27 prevents the write control signal WS from becoming active. Since it is delayed by
It is possible to prevent the precharge operation time 'rp from overlapping the write operation time Tw. As a result, the precharge current and the current generated by the write operation can be separated, and since no direct current flows, voltage drop in the power supply line and noise generation are suppressed, malfunctions are prevented, and stable operation is obtained.

In addition, although FIG. 4 shows the circuit configuration when each signal is a positive logic, in the case of a negative logic, a NOR gate 3θ is provided in place of the Nant gate 26 as shown in FIG. good.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a random access memory that can prevent malfunctions of internal circuits of the memory even if a write input signal is input at the same time as or immediately after a change in address signal input.

[Brief explanation of the drawing]

Fig. 1 is a block diagram for explaining a conventional random access memory, Fig. 2 is a timing chart for explaining the operation of the circuit shown in Fig. 1 above, and Fig. 3 shows a malfunction in the circuit shown in Fig. 1 above. FIG. 4 is a circuit diagram for explaining a random access memory according to an embodiment of the present invention. FIG. 5 is a timing chart for explaining the operation of the embodiment. FIG. 7 are diagrams showing an example of the structure of the delay circuit shown in FIG. 4, respectively, and FIG. 8 is a diagram for explaining another embodiment of the present invention. M□1~Mmn...Memory cell, WLI □'WLm
...Word dislike, B Ll t B Ll ~B L
n HBLn = pit line, l5... precharge circuit, WI... write input signal, WS... pull-in control signal, 27... delay circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] In a random access memory having a memory cell for holding data, a word line for selecting the memory cell, a bit line for exchanging data with the memory cell, and a precharge circuit for precharging the bit line. . A random access memory characterized in that when writing data to the memory cell, the write input signal is delayed so that the writing is performed after the bit line nori-charging operation is completed.