JPS5641573A - Access system of memory circuit - Google Patents

Access system of memory circuit

Info

Publication number
JPS5641573A
JPS5641573A JP11451179A JP11451179A JPS5641573A JP S5641573 A JPS5641573 A JP S5641573A JP 11451179 A JP11451179 A JP 11451179A JP 11451179 A JP11451179 A JP 11451179A JP S5641573 A JPS5641573 A JP S5641573A
Authority
JP
Japan
Prior art keywords
precharge
time
data bus
signal
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11451179A
Other languages
Japanese (ja)
Other versions
JPS603701B2 (en
Inventor
Hideji Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54114511A priority Critical patent/JPS603701B2/en
Publication of JPS5641573A publication Critical patent/JPS5641573A/en
Publication of JPS603701B2 publication Critical patent/JPS603701B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To shorten an access time while setting sufficiently long times up to write and readout starts, by synchronizing the timing of the precharge start of an internal data bus with the rise of a latch control pulse signal. CONSTITUTION:To start the precharge of internal data bus IBUS simultaneously with the rise of latch control pulse signal ALE, time t3 is equalized to the time when the data signal of an address data bus is substituted with an address signal and the precharge when readout and write control signals RD and WR are active is made possible. Further, since time t3 is set sufficiently long, there is no need to set it long anew. Therefore, the access time can be shortened by the pulse width of precharge signal IBPC by setting sufficiently long the time from the precharge end of the internal data bus to the data write and readout starts.
JP54114511A 1979-09-06 1979-09-06 Memory circuit access method Expired JPS603701B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54114511A JPS603701B2 (en) 1979-09-06 1979-09-06 Memory circuit access method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54114511A JPS603701B2 (en) 1979-09-06 1979-09-06 Memory circuit access method

Publications (2)

Publication Number Publication Date
JPS5641573A true JPS5641573A (en) 1981-04-18
JPS603701B2 JPS603701B2 (en) 1985-01-30

Family

ID=14639579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54114511A Expired JPS603701B2 (en) 1979-09-06 1979-09-06 Memory circuit access method

Country Status (1)

Country Link
JP (1) JPS603701B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182595A (en) * 1984-03-01 1985-09-18 Toshiba Corp Random access memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182595A (en) * 1984-03-01 1985-09-18 Toshiba Corp Random access memory

Also Published As

Publication number Publication date
JPS603701B2 (en) 1985-01-30

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