JPS5761337A - Pulse counter - Google Patents

Pulse counter

Info

Publication number
JPS5761337A
JPS5761337A JP13657280A JP13657280A JPS5761337A JP S5761337 A JPS5761337 A JP S5761337A JP 13657280 A JP13657280 A JP 13657280A JP 13657280 A JP13657280 A JP 13657280A JP S5761337 A JPS5761337 A JP S5761337A
Authority
JP
Japan
Prior art keywords
ram14
address
buffer
integrated value
designated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13657280A
Other languages
Japanese (ja)
Inventor
Makoto Chikuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13657280A priority Critical patent/JPS5761337A/en
Publication of JPS5761337A publication Critical patent/JPS5761337A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers

Abstract

PURPOSE:To largely reduce the number of elements to be used, by commonly using an adder which operates as a counter, an RAM, a buffer for reading and buffer for presetting. CONSTITUTION:When an edge of a pulse signal is detected by an edge detection circuit 111, writing on the prescribed address of an RAM14 is performed by adding 1 to the already written integrated value on the prescribed address of the RAM14. Then, the number of pulse signals corresponding to the integrated value which is desired to read is designated to a control circuit 15. The address of the RAM14 corresponding to the number is designated in the control circuit 15. From the RAM14, the integrated value stored on the address is read out and is transmitted to a buffer 16 for reading with time division of timing which does not select pulse signals. After that, the value is sent to an operational section 18.
JP13657280A 1980-09-30 1980-09-30 Pulse counter Pending JPS5761337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13657280A JPS5761337A (en) 1980-09-30 1980-09-30 Pulse counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13657280A JPS5761337A (en) 1980-09-30 1980-09-30 Pulse counter

Publications (1)

Publication Number Publication Date
JPS5761337A true JPS5761337A (en) 1982-04-13

Family

ID=15178389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13657280A Pending JPS5761337A (en) 1980-09-30 1980-09-30 Pulse counter

Country Status (1)

Country Link
JP (1) JPS5761337A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970319A (en) * 1982-10-15 1984-04-20 Yokogawa Hokushin Electric Corp Counter
EP0428047A2 (en) * 1989-11-14 1991-05-22 National Semiconductor Corporation Ram based event counter method and apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51378A (en) * 1974-06-19 1976-01-06 Tokyo Shibaura Electric Co PARUSUKEI SUSOCHI
JPS5286746A (en) * 1976-01-14 1977-07-19 Hitachi Ltd Pulse count readout control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51378A (en) * 1974-06-19 1976-01-06 Tokyo Shibaura Electric Co PARUSUKEI SUSOCHI
JPS5286746A (en) * 1976-01-14 1977-07-19 Hitachi Ltd Pulse count readout control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970319A (en) * 1982-10-15 1984-04-20 Yokogawa Hokushin Electric Corp Counter
EP0428047A2 (en) * 1989-11-14 1991-05-22 National Semiconductor Corporation Ram based event counter method and apparatus

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