JPS603701B2 - Memory circuit access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an access method for a memory circuit in which address signals and data signals are transmitted and received in a time-division manner via the same signal transmission line.

As the functionality of microprocessors improves, the address space required also increases year by year.

However, due to limitations on the number of pins on a package, some devices are using common address pins and data pins.
This system has the disadvantage that access time is long because a coded address signal for specifying the address of the memory cell array and a data signal for writing or proposing data are sent and received in a time-division manner. FIG. 1 is a conceptual diagram of a memory circuit using a method of multiplexing address signals and data signals.

In the figure, 1 is an address/data bus, 2 is a latch circuit, 3 is a memory cell, and SW to SW4 are switches.
ALE is a latch control pulse signal for the address latch circuit, which allows the address signal to be input into the memory circuit. m
The PC is a precharge signal of the internal data bus IBUS,
Precharging of the internal data bus BUS is started from the rise of this signal. RD and WR are input and write control signals, respectively. Conventionally, the timing of these signals was set as shown in FIG. In this timing chart, t., et al. It is desirable that t3 be sufficiently large, but if an attempt is made to shorten the access time, the time lag between the end of precharging the internal data bus and the start of writing and data transmission tends to become severe. If t is increased, the access time becomes longer, so t
, must be made as small as possible, but usually I
Since the BPC signal is generated using a delay circuit inside the IC, the pulse width is unstable and it is dangerous to reduce t. This invention makes it possible to shorten the access time in a memory circuit that multiplexes address signals and data signals as described above while taking a sufficiently long time from the end of precharging the internal data bus to the start of writing and issuing. This provides an access method for memory circuits.

The method of the present invention is characterized in that the timing of starting precharging of the internal data bus is synchronized with the rising edge of the latch control pulse signal, and a timing chart thereof is shown in FIG.

What requires attention here is the size of t3. In the case of FIG. 3, precharging of the internal data bus IBUS starts at the same time as the latch control pulse signal ALE rises, so if the RD or WR signal is active at this time, precharging cannot be performed. . However, since the time t3 coincides with the time when the data signal of the address/data bus is replaced with the address signal, and this time should originally be sufficiently long, there is no need to make t3 large again. In this manner, according to the method of the present invention, it is possible to take a sufficiently long time from the end of precharging the internal data bus to the start of data writing and logical output, and moreover, the time is approximately equal to the pulse width of the precharge signal field PC. Access time can be shortened.

[Brief explanation of drawings]

Fig. 1 is a conceptual diagram of a memory circuit that multiplexes address signals and data signals, Fig. 2 is a timing chart showing the conventional access method, and Fig. 3 is a timing chart showing the access method of the present invention. be. 1...address/data bus, 2...latch circuit, 3...
Memory cell, IBUS...internal data bus, ALE/
...Latch control pulse signal, IBPC...Internal data bus precharge signal. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In a memory circuit configured to transmit and receive an encoded address signal for specifying an address of a memory cell array and a data signal indicating write or read data in a time-division manner via the same signal transmission line, reading and writing of the memory circuit are performed. An access method for a memory circuit characterized in that access is performed by synchronizing the start timing of precharging of an internal data bus necessary for the above with the rising edge of a latch control pulse signal of an address latch circuit for specifying an address of the memory cell array. .