SU1455363A1 - Buffer storage - Google Patents

Abstract

The invention can be used to build buffer storage devices for information processing systems. The purpose of the invention is to increase the reliability of the device. The device contains a memory block 1 with information inputs 2 and outputs 3, a counter 4, the outputs of which are connected to the address inputs of block 1, a reversible counter 5, the contents of which determine the occupied memory size, a decoder 6 connected to the counter 5, at the outputs of which the signals of the memory appear freely and the memory is full, register 7, flip-flop 8, adder 9 modulo two, driver 10 pulses, elements 11 and 12, mode input 13, synchronization input 14. If trigger 8 is in O, then in counter 4 there is a read address, and in register 7 it is the write address. If trigger 8 is in O, then in the counter 4 is the address of the record, and in register 7 - the address of the read. The adder 9 and driver 10 exchange data between counter 4 and register 7 in order to enter the required address into counter 4 in accordance with the mode signal at input 13 and the state of trigger 8. Elements 11 and 12 generate read and write pulses for block 1 and addition and subtraction pulses for counter 5. 2 Il. (L

Description

The signal change in input 13 is time-readable for data from memory block 1, M, sufficiently enough for the trigger; the signal level at input 13 is changed. Neither flip-flop 8 at the counting input is high. In this case, a modulo-two modifier two appears, forming a signal level at the output of the adder-gel 10.

If at the moment of arrival of a low signal at input 13, trigger 8 is in a single state, i.e. counter 4 stores the current reading address, then at the output of modulator 0 modulo two a high level of the signal appears, according to which

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9 modulo two, by which a pulse is formed by the shaper 10 and the contents of register 7 are copied to counter 4, and the contents of counter 4 to register 7 and changed to the opposite state of trigger 8 "This connects to the address inputs of memory block 1 of the current read addresses. The incoming delay relative to the change in the level of the signal at input 13 is the signal at input 14 through

rover 10 will generate a pulse that rewrites the contents of register 7 1a counter 4, and the contents of counter

When reading data from memory block 1, the signal level at input 13 changes to high. In this case, a high level of signal appears at the output of

9 modulo two, by which a pulse is formed by the shaper 10 and the contents of register 7 are copied to counter 4, and the contents of counter 4 to register 7 and changed to the opposite state of trigger 8 "This connects to the address inputs of memory block 1 of the current read addresses. The incoming delay relative to the change in the level of the signal at input 13 is the signal at input 14 through

Element 11 at the input of gating — memory block 1 provides reading of data from memory block 1 to outputs 3 of the device. The falling edge of the signal at input 14 modifies the contents of the reversible counter 5 (subtracts one) and modifies the current read address in counter 4. If a read operation is to be performed in the next cycle, the state of the signal level at input 13 does not change. Subsequent data writing and reading cycles are performed similarly.

I

The output signals of the reversible counter 5 are fed to the decoder 6, which forms on the outputs 5 and 16 of the display signals the state of the buffer is empty

device, the reset inputs of the reversible counter and the counter are combined and are the device installation input, trigger, first and second elements AND, characterized in that, in order to increase the reliability of the device, it contains a register of a pulse driver and an adder

IQ is modulo two, with the first inputs of the first and second elements I connected to the counter input of the counter, the outputs of which are connected to the address inputs of the memory block and information inputs of the register, the installation input of which is connected to the input of the installation of the counter and the input of the trigger, direct output which is connected to the second input of the first ale The buffer is full, controlling the operation of the 2A and the first input of the adder for that receiver and transmitter of information.

Claims (1)

Invention Formula module two, the second input of which is the device mode input, the inverse trigger output is connected to the second input of the second element I, the output of which is connected to the write input of the memory unit and the fold input of the reversible counter, the input of which is read into the memory input and output the first element And, the output of the modulo two is connected to the input of the counter and the input of the pulse shaper, the output of which is connected to the counting input of the trigger, to the input of the register entry and the input of the record counter. A buffer memory containing a memory block whose information inputs and outputs are corresponding to the information inputs and outputs of the device, a reversible counter whose outputs are connected to the inputs of the decoder, the outputs of which are the device indication outputs, the counter whose clock input is sync input The device, the reset inputs of the reversible counter and the counter are combined and are the input of the device installation, the trigger, the first and second elements AND, characterized in that, in order to increase the reliability of the device, it contains a register, a pulse driver and an adder modulo two, the first inputs of the first and second elements AND are connected to the counter input of the counter, the outputs of which are connected to the address inputs of the memory unit and the information inputs of the register, the installation input of which is connected to the input of the installation of the counter and the input of the trigger, whose direct output is connected to the second input of the first element And and the first input of the adder on module two, the second input of which is the device mode input, the inverse trigger output is connected to the second input of the second element I, the output of which is connected to the write input of the memory unit and the addition input of the reversible counter, the input of which is read from the memory unit and the output of the first element And, the output of the adder modulo two is connected to the input of the counter mode and the input of the pulse shaper, the output of which is connected to the counting input of the trigger, to the input of the register entry and the input of the record of the counter. Xue e-. "