RU1816326C - Video controller - Google Patents

Abstract

The invention relates to automation and computer engineering. Its use in video pre-processing means allows to increase the speed by eliminating interference in the form of small objects in the original image. The video controller contains a state register 1, a digital-to-analog converter 7, a video camera 9, a comparator 10, an image memory unit 14, a pulse selector 15, an element number counter in line 16, a threshold level generator 27 and a microcomputer bus controller 28. Thanks to the introduction of a signal level change detector 11, the register of the element number in line 17, the clock generator 18, the And element 20. The OR elements 19, 22, 23 of the trigger 21 and the delay generator of the recording of the coordinates of the differential drop 29 in the video controller implements an algorithm for Only segments of the image whose sizes are not less than specified are written by memory to the memory. 1 wp 3 ill.

Description

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ABOUT

The invention relates to automation and computer technology, specifically to technical means for pre-processing a video image and can be used to calculate coordinates and identify moving objects by calculating the first moments, areas and other features of binary figures based on the accepted universal representation of video data.

The aim of the proposed technical solution is to increase speed by eliminating interference in the form of small objects in the original image.

In FIG. 1 shows a functional diagram of a video controller; in FIG. 2 is a diagram of the formation of boundaries when recording an image frame in the memory of the video controller, where it is indicated: a - scanning line, b - clock pulses, c - image field, d - video signal and data representation in the memory; in FIG. 3- block diagram of a typical computer work program with data. video controller.

The functional circuit of the video controller includes: state register 1, threshold register 2, address selector 3, delay code register 4, address register 5, data register 6, digital-to-analog converter (DAC) 7, delay counter 8, video camera 9, comparator 10, change detector signal level 11, containing a trigger for synchronously recording changes to comparators, an EXCLUSIVE OR element, a delay counter control trigger 12, address counter 13, an image memory unit 14, clock pulses 15 and an element number counter in line 16, which with direct assignment, they realize the function of a signal conditioner, end of line, register of element number in line. 17, clock generator 18, element И И 19, element И 20, trigger 21, elements OR 22 and 23, microcomputer bus 24 (in this particular embodiment the micro-computer bus Electronics-60 was used, implemented on microprocessor set MPK588), internal bus addresses and controls 25 and internal data bus 26. The threshold register 2 and the DAC 7 form a threshold level former 27; address selector 3, address register 5, data register 6 and address counter 13 form a microcomputer bus controller 28; a delay code register 4, a delay counter 8, and a control trigger for the delay counter 12 form a delay driver for recording the coordinates of the differential drop 29.

The address selector serves to communicate the state register 1, threshold register 2, delay code register 4, address register 5 and computer data register 6 implemented on the IPC588 base via the IPC bus 588 in accordance with its interface. Each of

of the listed registers has its address on the IPC 588 bus. The address selector receives the current address from the IPC bus 588 and decrypts it. If it matches one of the specified registers, then the selector

addresses allows writing (or reading) data from the IPC bus 588 to the specified register.

The registers of address 5 and data b are intended for communicating with a computer with the memory module 5 when it is in storage mode. At the same time, for reading or writing information, the required address and sign (write / read) are recorded in the address register, and the register

0 data 6 serves as a source or receiver of information.

The combination of the outputs of the address register 5 and the address counter 13 in the address and control bus 25, as well as the combination of the outputs of the element number register in line 17, memory unit 14 and data register 6 in the data bus 26 is possible due to the use of elements with three states output.

0 The video controller operates as follows.

In the initial state, the video controller is in the storage mode of the image frame located in its memory.

5 To write to the memory of the video controller of the current frame, the on-code is entered into state register 1, which is fed to input 21. The trailing edge of the closest frame clock signal is turned on.

0 is transmitted to the output of trigger 21 and starts the clock generator 18, which initiates the conversion and recording of the current image frame in the memory unit 14. The leading edge of the next frame sync 5 pulse, using the elements AND 20 and OR 19, generates a reset signal, according to which the register state 1, the readiness indicator is entered, the power-on signal is reset, and the address counter 13 is reset. The readiness indicator indicates that the video controller has entered storage mode.

The video signal coming from the video camera 9 is converted by the comparator 10 to

5 binary representation. The comparation threshold is contained as a code in the register of threshold 2 and is generated by a digital-to-analog converter 7. The video signal is also fed to the input of the clock selector 15, which

is intended to extract frame and horizontal sync pulses from a video signal.

At the time of starting the clock generator 18, the delay counter 8 is in parallel recording mode and contains a number from the register of the delay code 4. When the video signal level changes, the comparator 10 switches and the signal level change detector 11 generates a pulse, which overwrites the contents of the element number counter in line 16 to the register of the element number in line 17 and inverts the state of trigger 1.2, which leads to the transfer of the delay counter 8 to the sequential count mode, since the decrement mode is implemented in the delay counter, then its contents begin to decrease in pulses from the clock generator 18. If the video signal level does not change in a time equal to the number of clocks recorded in the register of delay code 4, then the delay counter will count to zero and the pulse that will reset trigger 12 is outputted and initiates the recording of the contents of the register of the element number in line 17, which currently contains the abscissa of the segment boundary (lines 2 and 3 in FIG. 2), in the memory unit 14 at the address located in the address counter 13. Moreover, after records, counter contents Dres 13 inkremen- tiruets. If the video signal level changes before delay counter 8 reaches zero, then the pulse from change detector 11 of trigger 12 will be returned to its original state, and delay counter 8 will be transferred to parallel recording mode and the code register number will be written to it again delays 4. In this case, a pulse at the output of the delay counter 8 does not occur and the abscissa of the segment boundary (line 1 in Fig. 2) is not recorded in the memory unit 14.

The process of recording a video frame in memory is shown in FIG. In this case, the delay is equal to two clock pulses. Since the length of the upper segment of the first line is equal to one clock pulse, this segment is not stored in the memory. The length of the lower segment in the second and third lines is more than two, and this segment is recorded in the memory.

When presenting information in memory, zero indicates the end of the current line. The number of zeros determines the number of the current line in the frame, or, in other words, the ordinate of the segment border element. The end-of-line signal is generated from horizontal synchrometry. At the same time, the counter of the element number in line 16 is reset.

after which its contents are rewritten in the register of the element number on line 17 and then to the memory unit 14.

The work program of the computer with this video deocontroller, a block diagram of which is shown in FIG. 3, contains: module 1 — write to the register of the delay code of the specified minimum allowable size of segments, module 2 — write the binarization threshold into the threshold register, module 3 — record the reading of the current frame in the video controller, module 4 — wait for the end of reading and convert the current frame images in the format described above, module 5

5 - reading the received frame from the memory of the video controller and processing it in order to solve the problem, module 6 - either switching to reading the next frame or completing work with the video controller.

In this way, the video controller uses the principle that allows recording at the sampling stage of the video signal only the coordinates of the segments of segments 5 whose sizes are not less than those programmed in the delay code register 4. In this case, the ordinate boundary point will be the line number and the abscissa will be the number of clock pulses from the beginning of the current

0 lines until the video signal level changes.

Claims (1)

SUMMARY OF THE INVENTION 1. A video controller comprising a video camera, a clock selector, a threshold level generator, a comparator, an element number counter in a line, an image memory unit, a status register and a microcomputer bus controller, the video camera output is connected to the input of the clock pulse selector, the first output of which connected to the control input of the counter of the number of the element in the line, the output of the threshold level driver is connected to the first input of the comparator, which is so that, in order to improve performance due to roubleshooting interference in the form of small objects in the original image, a video controller administered varying signal level detector, clock 0 generator, first or third OR elements, AND element, trigger, register of the element number in the line, and a delay shaper for recording the coordinates of the differential drop, including a delay code register, a 5 delay counter and a trigger for controlling the delay counter, whose inverse output is connected to it information input, and the direct output is connected to the enable input of the delay counter, the installation inputs of which are connected to the outputs register of the delay code, the output of the camera is connected to the second input of the comparator, the output of which is connected to the first input of the detector for changing the signal level, the output of which is connected to the clock input of the trigger for controlling the delay counter in the delay generator of recording the coordinates of the difference in brightness and the first input of the second OR element, the output which is connected to the first control input of the element number register in the line, the first information inputs of which are connected to the outputs of the element number counter in the line, the output of the counter the holders in the delay generator of recording the coordinates of the differential drop is connected to the input of the zeroing trigger for controlling the delay counter in the generator of delay of the recording of the coordinates of the differential brightness and to the first input of the third OR element, the second inputs of the second and third elements OR are connected to the first output of the clock selector, the second output of which is connected to the first input of the And element and the clock input of the trigger, the output of which is connected to the second input of the And element and the input of the clock generator, the output of which is connected to the account the input of the counter of the number of the element in the line, the second input of the detector for changing the signal level and the counting input of the delay counter in the former of the delay for recording the coordinates of the brightness difference, the output of the AND element is connected to the first input of the first OR element, the second input of which is the status register information input information inputs of the threshold level driver, information inputs of the delay code register in the driver delays in recording the coordinates of the difference in brightness and the first and third information inputs of the microcomputer bus controller form the microcomputer bus. the fourth information inputs of the microcomputer bus controller are combined with the corresponding second information inputs of the element number register in the line and the information inputs of the image memory block, the address inputs of which are connected to the address outputs of the microcomputer bus controller, the output of the third element OR is connected to the second control input of the element number register in line and the first control input of the microcomputer bus controller, the output of the first OR element is connected to the second control input of the microcomputer bus controller M and the first control input of the state register, the output of which is connected to the information input of the trigger, the first, second and third control outputs of the microcontroller bus of the microcomputer are connected respectively to the control input of the threshold level driver, the second control input of the status register and control the input to the register of the delay code in the shaper delay recording coordinates of the differential brightness, 2, The video controller according to claim 1, with the exception of the fact that the threshold level driver comprises a threshold register and a digital-to-analog converter connected in series, the output of which is an output of the driver, the information and control inputs of the threshold register are of the same name shaper inputs L114 56 78 9 10 FIG 2 (Start j Writing a specified minimum allowable segment size 6 register delay code Entry threshold entry 6 register threshold Reading the received frame from the memory of the Video Controller and its processing in order to solve the problem ya . Reading, avogo frame , Yet G Stop}