SU1201841A1 - Interface for linking process control computer with peripheral units - Google Patents

Abstract

1. - DEVICE FOR ASSOCIATING. CONTROL COMPUTER MACHINE WITH PERIPHERAL DEVICES, containing the exchange register, input and output switches, buffer register, priority block, and the successive information input and output of the exchange register connect the yen with the input and output information buses and the information inputs and output information of the exchange register connecting the yen with the input and output information buses and the information boards and the output information registers connected yen to the input and output information exchange boards and the informational input and output of the exchange register that connect the yen to the input and output information circuits of the yen respectively. computer, parallel information. The output of the exchange register is connected to the first information input of the input switch, the second information input of which is connected to the output w another entry of the peripheral device, the 9LOAD of the input switch is connected via the buffer register to the information input of the output switch, the first code of which is connected to the input readout bus of the peripheral device; the second output of the output switch is connected to the parallel information input of the exchange register and to the information input of the priority block that differs the fact that, in order to increase the speed of the device, a synchronization block, a register block of settings, a comparator, a timer, an interrupt block and a block are entered into it to the microprogram control, where the synchronization output of the control subtractive machine is connected to the input of the synchronization unit, the first output of which is connected to the first synchronization input of the microprogrammed control unit, the second synchronization input of which is connected to the output of the timer, which output is connected to the timestamp input of the peripheral device and the synchronization input the priority block, the second output of the synchronization block — the timer synchronization input, the second output of the output switch — with the input of logical services of the firmware control, timer, comparator and setting register block, and the outputs of the comparator interrupt block and the first output of the priority block, respectively, with the first, second and third address inputs of the firmware control unit, the first and second outputs of the exchange direction of the microprogram control unit, respectively, connected to the control The inputs of the output and input switches, and the outputs the readiness of setting readings, the resolution of setting comparisons, the activation of the timer of the microprogrammed control unit laziness connected respectively to strobe inputs setting register block, a comparator and a timer, the first and second outputs of the micro modal block

Description

the program control unit is connected to the installation inputs of the interrupt and priority blocks, the trigger output of the microprogram control unit is connected to the peripheral device's synchronization, the output of the settings register unit is connected to the comparator code input 5, the output of which is connected to the peripheral input mode selection input of the peripheral output terminal the device is connected to the backup input of the priority block, the code output of which is connected to the write input of the interrupt block;

2. The device according to claim 1, characterized in that the microprogram control unit comprises a group of pulse drivers, an operational buffer memory, a group of AND-OR elements, a group of state decoders, a write and read signal generator, a constant buffer memory, a driver synchronization signals, a read clock counter, a decoder of clock counts, the input of logic conditions of the firmware control block is connected to the information input of the operational buffer memory, the write write inputs of which are connected dinene with the corresponding outputs of the write and read signal generator, the inputs of which are connected respectively to the outputs of the synchronization signal generator and the clock decoder

readout, the output of which is connected to the first inputs of the AND-OR group and the installation input of the read clock counter, the output of the synchronization signal generator is connected to the gate inputs of the read clock counter and the group pulse drivers, the output of the read clock counter is connected to the inputs of the read clock decoder and constant buffer memory., the output of which is connected to the first inputs of the decoders of the states of the group, the second inputs of which are connected to the output of the operational buffer memory, the outputs of the decoder At the same time, the state of the group is connected to the second inputs of the elements AND-OR groups, the outputs of which are connected to the inputs of the states of the pulse shapers of the group, the outputs of which are the first and second outputs of the exchange direction, the outputs of readout of setting, resolution comparison of settings, timer start, first and the second mode of the outputs and the triggering output of the microprogram control unit, the first, second and third address inputs of which are connected to the third, fourth and fifth inputs of the AND-OR group elements and the first and second inputs of the sync drivers are respectively the first and second sync inputs of the firmware control block.

The invention relates to computing and can be used to enter information about the parameters of objects into control computing machines (UVM), after which the outputs of the UVM processing results can be output to several peripheral devices. As UVM, electronic keyboard computational maps can be used, for example.

The circuit of the invention is to increase the speed of the device, which allows to expand the functionality of the device by using it in real time systems.

Fig, 1 shows the block diagram of the proposed device; in fig. 2 is a block diagram of the firmware control unit.

The device contains a processor

1 UVM, register 2 exchange, switch 3 input, output 4 records of peripheral devices (PU): buffer register 5, switch 6 output. 3 output read PU, block 8 synchronization, block 9 firmware, synchronous input 10 PU, block 11 interrupts, block 12 registers settings, comparator 13, input 14 select modes PU, timer 15, input 16 - time stamp PU, block 17 priorities , exit 18 is a sign of priority of PU. The firmware control unit (Fig. 2) contains an operational buffer memory 19, a group of pulse generator 20, a group of elements 21 AND-OR, a group of decoders 22 states, a permanent buffer memory 23, a writer and read signal generator 24, a decoder of 25 cycles readout; counter 26 read cycles; driver 27 of synchronization signals. The device is designed for both the liver fast data exchange peripheral device with a central processor UVM. With this, c. The purpose of increasing the speed is to allow tolerance control and software control of the periphery, controlling the color of printing on the printing device. For example, an electronic keyboard on a computational bus is used as a central processor. Electronics BZ-21, the memory of which is a closed dynamic ring, consisting of three internal registers. The memory ring is broken at the junction of two registers and in the gap is entered from exchange register 2, through which access to any area of memory is provided. At the same time, information is recorded and read byte-by-byte. The device works as follows. The program of the device is stored in the memory of the ACU (not shown) and in the exchange register 2. The control signal from block 9 reads the program of operation of the device from the exchange register 2 through switches 3 and 6 and the buffer register 5 and block 9, and then it is entered in a certain sequence into blocks 12, 15 and 17. The program specifies: the number of information sensors and the program of their 1 survey: the address of the peripheral device; the values of the settings for the block 12 lierHCTpoB settings; temporary in-. intervals for timer 15; priority sensors. The synchronization unit 8 performs the synchronization of the device pulses to the synchronizing pulses of the processor 1 of the ACU. The information is entered into the device as follows. At the output 18 of the priority indicator of the PU, a signal is generated that characterizes the given PU. The unit 17 analyzes the priority and issues signals to the microprogram control unit 9 and the interrupt unit 11, which ensure the operation of the device when entering information. The priority signal from block 17 goes through the interrupt block 11 to the microprogram control block 9, which issues a signal to the priority block 17 on the removal of information from the control unit with the highest priority. The priority block 17 after this signal evaluates the highest priority of the remaining external devices that sent the exchange request, and signals the sign of the device with the highest priority. Timer 15 generates timestamps on both block 9 and PU output 16). In accordance with these labels, block 9 generates control signals that are fed to input 10 to control the exchange of information. Information from the control unit comes from the information input 4 through the input switch 3 to the buffer register 5. At the command from block 9, switch 6 of the switch connects buffer register 5. Then, the signal from control block 9 records information to the comparator 13. Comparator 13 compares ( Tolerance control of incoming information with settings that are in block 12 of memory; :: registers and, consequently, it is determined that the incoming information is exceeded (underreporting) with respect to the lower or upper permissible limits. There, the tolerance control in the comparator 13 produces signals for block 9 and for an external printing device (output 14), which sets the color of the print on the external printing device. the tolerance control did not pass, then at the command from block 9, the switch 6 of the switch connects the output of buffer register 5 to information output 7, then, at command 9, the signal Scchangan appears at the input of 10 status indicators of the PU. The information printed on the printer is printed in red, which is set by the signal from input 14. If the incoming information passed the additional control, then block 9 issued a command for switch 6 of the output to connect the output of buffer register 5. to the information parallel input of exchange register 2, from where The information is entered into the processor 1 of the ACU, where it is processed in accordance with a predetermined program. After the processing of the received information is completed, the results of the output via the exchange register 2, the input switch 3 to the buffer register 5. At the command of unit 9, the output switch 6 connects the output of buffer register 5 to the information output 7. Then the synchronous input 10 receives the Read and peripheral signal The printer starts reading this information. In addition, after tolerance testing of the comparator 13 at the input 14 of the PU, the print color for the peripheral printing device is set.

The firmware control unit 9 operates as follows.

From the synchronization circuit 27, the sync signals are fed to a clock counter 26. The clock counter state 26 is a control to pick up a microcommand from a fixed buffer memory 23.

A decoder of 25 clocks is connected to the group of elements 21 AND-OR and a driver of 20 functional signals by its outputs, the recorder 24 of the recording and matching signals is designed so that when the synchronization signals arrive from the generator of the synchronization signal 27, the state of the decoder is 25 clocks. During the first clock cycles, the Write signal for the buffer memory 19 is generated, and during the subsequent clock cycles the Read signal is generated.

On the Record signal, initial information from the information bus is recorded on the first clock cycles. On a read signal, the information is read out by the operational buffer memory 19 and fed to a group of decoders 22 states. On each decoder decoder 22, information is stored from a fixed buffer memory 23, which is a micro-command of control, taking into account the initial information specified by the operator.

At each clock cycle at the output of the imaging unit, 20 functional I / O signals appear, at a given output, a control signal, by means of which the system is controlled and operated according to a predetermined algorithm. As peripheral devices, sensors are used, from which information and a printing device are taken.

To SflOKan bykhod. 6 5

Claims (2)

1 . - DEVICE FOR COUPLING - COMMUNICATIONS OF A CONTROL COMPUTER MACHINE WITH PERIPHERAL DEVICES, comprising an exchange register, input and output switches, a buffer register, a priority block, the serial information input and output of the exchange register being connected respectively to the input and output information buses of the control computer, the parallel information output of the exchange register is connected with the first information input of the input switch, the second information input of which is connected to the output bus of the recording peripheral device VA, the output of the input switch through the buffer register is connected to the information input of the output switch, the first output of which is connected to the input bus of the peripheral device, the second output of the output switch is connected to the parallel information input of the exchange register and to the information input of the priority unit, characterized in that , in order to improve the speed of the device, a synchronization block, a block of setup registers, a comparator, a timer, an interrupt block and a firmware control block are introduced into it; stroke synchronization control subtraction machine connected to the input sync block, the first output of which is connected to the first input of the synchronization microprogram control, a second clock input connected to the output timer with an output connected to the input timestamp pe- _ With a * peripheral device and a priority block synchronization input, the second output of the synchronization block is the timer synchronization inlet, the second output of the output switch is the input of the logical conditions of the microprogram control block, timer, comparator and block of setting registers, and the outputs of the comparator interrupt block are the first priority block output - respectively, with the first, second and third address inputs of the microprogram control unit, the first and second outputs of the exchange direction of the microprogram control unit are connected to correspondingly with the control inputs of the output and input switches, readiness to read the settings, enable comparison of settings, enable the timer of the firmware control unit are connected respectively to the gate inputs of the settings register block, comparator and timer, the first and second mode outputs of the microSU block., „1201841 program control connected to the installation inputs of the interrupt and priority blocks, the trigger output of the firmware control block is connected to the clock input of the peripheral device, you od setting register block coupled to a code input; comparators, - the output of which is also coupled to an input mode selection, operation of the peripheral device output characteristic ^ priority peripheral device soei union of interrogating input priority block, coded output is connected to an interrupt input recording block '. 2. The device according to π. 1, characterized in that the microprogram control unit contains a group of pulse shapers, an operative buffer memory, a group of AND-OR elements, a group of state decoders, a driver of write and read signals, a constant buffer memory, a driver of synchronization signals, a counter of read clocks, a decoder of read clocks moreover, the input of the logical conditions of the microprogram control unit is connected to the information input of the operational buffer memory, the read entries of which are connected to the corresponding the outputs of the write and read signal generator, the inputs of which are connected respectively to the outputs of the synchronization signal generator and read clock decoder, the output of which is connected to the first inputs of the AND-OR group elements and the setup input of the read clock counter, the output of the synchronization signal generator is connected to the strobe inputs of the clock counter of readings and pulse shapers of the group, the output of the counter of read clocks is connected to the inputs of the decoder of the read clocks and a constant buffer memory output, whose output is connected to the first inputs of the group state decoders, the second inputs of which are connected to the output of the RAM buffer, the outputs of the group state decoders are connected to the second inputs of the AND-OR group elements, the outputs of which are connected to the state inputs of the group pulse generators, the outputs of which are respectively, the first and second outputs of the exchange direction, readiness outputs for reading the settings, enabling comparison of settings, turning on the timer, the first and second mode outputs and the start repentieth output of the microprogram control, the first, second and third address inputs of which are connected with the third, fourth and fifth inputs of the AND-OR groups, and the first and the second input of the synchronization signals are respectively first and second inputs of synchronization microprogram control unit.