SU1562921A1 - Device for interfacing information source and receiver - Google Patents

Abstract

The invention relates to computing and can be used as a buffer memory device. The aim of the invention is to increase the reliability due to the hardware separation in time of the coincident write and read commands. The device contains a pulse distributor, a memory unit, a register, a reversible counter, a write counter, a read counter, a fill decoder, a zero decoder, two groups of AND elements, a group of OR elements, two AND elements, and two delay elements. 3 il.

Description

The invention relates to computing and can be used as a buffer memory device.

The aim of the invention is to increase the reliability due to the hardware separation in time of the coincident write and read commands.

Figure 1 presents the block diagram of the device; FIG. 2 is a functional diagram of the pulse distributor in FIG. 3 - time diagram of the operation of the pulse distributor.

The device (Fig. 1) contains the first 1 and second 2 elements AND, the register 3, the distributor 4 pulses, the reversible counter 5, the reading counter 6, the write counter 7, the first 8 and second 9 delay elements, the decoder 10, the decoder 11 zero, first 12 and second 13 groups of elements AND, group of elements OR 14, memory block 15, synchronization inputs of reading 16 and writing 17, information input 18 and inputs 19 and 20 and outputs 21-24 of the pulse distributor.

The pulse distributor (FIG. 2) contains the elements HE 25 h 26, the triggers 27-30, the single-switches 31 and 32, and the trigger 33.

The device works as follows.

By turning on the power in the device, a pulse is generated. The initial reset sets the initial state (zero) register 3, valve 4 (triggers 27-30 and 33), reversible counter 5, read counters 6 and write 7, the output of the decoder 11 is prohibiting the potential blocking element And 1, and at the output of the decoder 10 - the resolving potential, the opening element And 2, from the output 21 of the distributor 4 enters the inputs of the first group of elements And 12 the inhibitory potential, and from the output 22 of the distributor 4 - to

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the inputs of the second group of elements And 13 allow the potential, thereby connecting the write counter 7 to the address inputs of the memory block 15, therefore the device is prepared to receive information from the source.

The recording clock signal from the device input 17 records the information from the device 18 input with a parallel code into register 3 and modifies the first address at the output of the record meter 7, which receives the address inputs of the memory block 15 through a group of elements 12, open

resolution potential from output 22 i,

distributor 4, and a group of elements

OR 14. In addition, the recording clock signal from the device input 17 is fed to the input 20 of the distributor 4, which generates a write pulse at the output 24, which is input to the increase in the account of the reversing counter 5, increasing its state by one, and also through delay element 9, rewriting of information from register 3 into memory block 15. The inhibitory Potential is removed from the output of the decoder 11, thereby permitting the passage of read signals to the device.

When the next code arrives at the device input 18 and the synchronization signal at input 17, the record counter 7 is incremented by one, a second address is set at the address input to which information from register 3 is overwritten to memory block 15 using a Record pulse from distributor 24 4. The same write pulse increases the state of the reversible counter 5 by one. Similarly, further information is filled with the memory block 15. When all the cells of the memory block 15 are filled, as evidenced by the filling of the reversible counter 5, the filling decoder 10 generates a signal, the blocking element AND 2 and thereby prohibits further recording of information in the memory block 15. The first read clock signal received at the device input 16 reads the information from the address of the counter 6, -c reading, removes the inhibitory potential at the input 17 and allows further recording of information into the device. The signal from the output of the decoder 10 may

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be issued to the source of information to the signal to fill the memory block 15 and block the issue of data to the input 18 of the device.

If the read sync signal arrives at the input 16 before the memory block 15, the write counter 7 and the reversible counter 5 are filled, respectively, with information, write clock signals and write pulses, a unit is written to the counter 6. From the output 23 of the distributor 4, the read pulse subtracts 5 from the contents of the reversible counter and, through the delay element 8, enters the input of the memory block 15, reads the information from the memory block 15 to the output of the device. The address at which the information is read is fed from the output of the reading counter 6 through the group of elements And 12, opened by the resolution potential from the output 21 of the distributor 4, and the group of elements OR 14.

When the next read clock signal arrives, a unit is added to the device input 16 in the counter 6, and the second control code is set at the address input of the memory block 15. From the output 23 of the distributor 4, the read pulse reduces the state of the reversible counter 5 by one and reads information at this address from the memory block 15 to the output of the device. At the completion of reading all information

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words stored in the memory block 15, the reversible counter 5 is set to the zero state, as a result of which the decoder 13 generates a signal, blocking element AND 1 and prohibiting the change of the state of the device according to the read signals received at the input 160 At the same time the signal from the output of the decoder 11 can be sent to the information receiver as a read-out signal (no information to read).

In the case when the write and read sync signals are simultaneously received at the inputs 16 and 17 of the device, the distributor 4 carries out the separation in time of the write and read cycles. At the same time, the information at input 18 is synchronized to input I7 and is recorded in register 3. After this, distributor 4 generates signals that are used to record ins

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words stored in the memory block 15, the reversible counter 5 is set to the zero state, as a result of which the decoder 13 generates a signal, blocking element AND 1 and prohibiting the change of the state of the device according to the read signals received at the input 160 be sent to the information receiver as a read-out signal (no information to read).

In the case when the write and read sync signals are simultaneously received at the inputs 16 and 17 of the device, the distributor 4 carries out the separation in time of the write and read cycles. At the same time, the information at input 18 is synchronized to input I7 and is recorded in register 3. After this, distributor 4 generates signals by which information from register 3 is recorded in memory block 15, and then information is read from it or, conversely, first reads information from memory block 15, and then rewriting information from register 3 to memory block 15. The order of the read and write cycles depends on the synchronization frequency.

With the simultaneous arrival of the read and write clock signals to the inputs 19 and 20 of the distributor, the triggers 27 and 28 are set to one because the inputs of these triggers are connected to a logical one. After this, the states of the triggers 27 and 28 are overwritten by the next pair of triggers 29 and 30 the leading edge of the synchronization frequency in the trigger 30 and the trailing edge of the synchronization frequency in the trigger 29. The one-vibration 31 and 32 pulses the required duration for reliable operation of the trigger irepa 33, the reversing counter 5 and the memory unit 15 of the device oystva pulse from the monostable 31 is fed to inputs of flip-flops in G 27 and 29, input 33 setting latch 1, the input account reduce down counter 5 and 8 through a delay element to the input of the read block memory 15. The impulse from the one-shot 32 is fed to the inputs of the installation in O of the trigger 33 | and trigger 28 and 30, the input increases

nor the account of the reversible counter 5 and | through the delay element 9 to the input of rewriting information of the memory block 15.

The sequence diagram of the operation of the pulse distributor (Fig. 3) is given for various combinations of input signals relative to the synchronization frequency.

Thus, the device receives and distributes information without distortion and eliminates the possibility of its loss by connecting the inputs of the reversible counter to the third and fourth outputs of the control signal distributor, which eliminates the simultaneous appearance of write and read pulses at the inputs of the reversible counter.

Claims (1)

Invention Formula A device for interfacing the source and receiver of information containing a memory unit, a pulse distributor, a write counter, a read counter, a reversible COUNTER, a fill decoder, a decoder zero, re 0 five five a gist, two elements AND, two delay elements, two groups of elements AND, a group of elements OR, the first input of the first element AND being the input of the device for connecting to the read output of the information receiver, the first input of the second element AND being connected to the input of the register and The Q input of the device for connecting to the output of the information source record, the group of information inputs of the register forms the group of inputs of the device for connecting to the group of information outputs of the information source, the group of information outputs of the device The memory forms a group of information outputs for connection to the group of information inputs of the information receiver, while the group of outputs of the reversible counter is connected to the groups of information inputs of the zero decoder and the descrambler 5 whose outputs are connected respectively to 5 second inputs of the first and second elements And the outputs of which are connected respectively to the first and second inputs of the start of the pulse distributor, the first and second synchronous outputs of which are connected respectively to the first inputs of the elements s of the first and second groups, the second inputs of which are connected respectively to the outputs of the reading counter and the record counter, the counting inputs of which are connected respectively to the outputs of the first and second elements AND, the outputs of elements AND of the first and second groups are connected respectively to the first and second inputs of the elements OR the outputs of which are connected to the group of address inputs of the memory block, the read and write inputs of which are connected respectively to the outputs of the first and second delay elements, the inputs of which are connected respectively to The third and fourth synchronization outputs of the pulse distributor, a group of information outputs of the register is connected to a group of 0 information inputs of the memory block, characterized in that, in order to increase the reliability due to hardware separation in time of the coincident write commands and reading, the third and fourth the pulse distributor sync outputs are connected to the increase and decrease inputs of the reversible counter, respectively.