SU1730630A2 - Device for interfacing source and receiver of information - Google Patents

Abstract

The invention relates to computing and can be used in the design of systems for collecting and processing information. The purpose of the invention is to improve the reliability of the device by providing hardware rejection of failed data blocks when working with blocks of variable length. Failures occur due to interference in the communication channel. The goal is achieved by introducing a device containing a memory block, a counter, a trigger, a decoder, two OR elements, two delay elements, a multiplexer and a one-shot. comparison schemes, register, additional trigger and decoder, two elements And 3 Il

Description

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The invention relates to computing, in particular, to devices for coupling the source and receiver of information, and can be used as a buffer memory device in information collection and processing systems.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 is a block diagram of the device; in fig. 2 and 3 - schemes of the trigger.

The device contains memory block 1, counter 2, trigger 3, decoder 4, elements OR 5 and 6, delay elements 7 and 8, multiplexer 9, one-shot 10, additional trigger 11, comparison circuit 12, register 13, And elements 14 and 15 , additional decoder 16, information inputs 17 and output 18, write enable output 19, write synchronization input 20, faulty block output 21, read enable output 22, initial setup (reset) input 23, and read synchronization output 24 of the device.

The trigger 3 in the first embodiment contains the counter 25 and the element NOT 26, in the second - the elements HE 27 and 28 and the trigger 29.

The device works as follows.

Before the start of operation, the signal at the reset input 23 is set to the zero state of the triggers 3 and 11 and the counter 2.

At the output of the trigger 11, i.e., at the output 21 of the alarm of the failed unit, there is a low level - there is no synchronization failure. Counter 2 is reset, so a high-level signal is present at the output of decoder 16. The low signal level at the forward output of the trigger 3, i.e., at the readout output 22, sets the memory block 1 to the write mode and prohibits the information receiver to request read data. High level CJ O ON CO O

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The level of the signal at the inverse of the trigger output 3, i.e., at the write enable output 19, permits the information source to handle data write requests.

The recorded data is fed to the input 17 of the device, accompanied by a signal at the synchronization input 20, which is fed through the element OR 5 to the synchronization input of the access of memory block 1 and records data from inputs 17 to block 1 at the address formed on counter 2. The falling edge the synchronization signal of the recording coming from the input 20 and passing through the element OR 5 is modified by the contents of the counter 2, i.e. one is added to its contents. When recording the first word of a data block, the information part of which indicates the number of information words in this block, i.e. the total number of words minus one, the contents of counter 2 is zero, which leads to the formation of a high level signal at the output of the decoder 16. Therefore, the first write synchronization pulse, inputted from input 20, records the word from input 17 not only in memory block 1, but also through element 14 into register 13. On the trailing edge of the first write synchronization pulse, the contents of counter 2 become one, At the output of the decoder 16, a low level signal appears that prohibits the passage of the next write synchronization pulse to the register 13 through the element 14. When writing a data block, the high resolution level at the output of the decoder 16 is present only in one case the contents of counter 2 is zero, i.e. when writing the first word of a data block. The first word of the block containing the code of the number of information words is recorded both in memory block 1 and in register 13. The remaining words of the data block are written in memory block 1 at the increasing addresses (starting from zero) formed by the counter 2.

When writing each information word, its content is analyzed in order to fix it by identifying the sign of the End of the block. This analysis is performed on decoder 4. In recording mode, the low level of the signal at the forward output of trigger 3, acting on the control input of multiplexer 9, provides a connection to the inputs of the decoder 4 information inputs 17. The input signal of the decoder 4 receives a single-vibrator 10 output which generates signals on the leading edge of the signal at the output of the element OR 5, which is delayed on the element

7 delays. When a sign appears at information inputs 17, the end of the block and its recording in memory block 1 at the time of gating the decoder 4 at its output

a positive polarity signal appears, which goes to an open element during recording (due to a high level from the inverse of trigger 3) AND 15. A high level signal acts on

0 control input of comparison circuit 12, allowing comparison of counter 2 and register 13. If there were no synchronization failures during recording of the data block (recording clock sync or no 5 outputs were lost), then at the time of recording the last information word of the block containing the End of block attribute, the contents the counter 2 is equal to the contents of the register 13, the output of the comparison circuit 12 keeps 0 with a low level, the trigger 11 remains in the zero state and the output 21 of the alarm system alarm of the failed block is kept low - the block is received without a failure synchronous izatsii. If while writing a block of data were

5 recording synchronization failures (i.e., the recorded data block is shorter or longer than it should be in comparison with the size specified in the first word of the block), then at the moment of recording the last information word

0, the contents of counter 2 are not equal to the contents of register 13, the output of the comparison circuit 12 is set to high (its operation is enabled by a signal from the decoder 4 passing through the element 15). Trig ger 11 is set to one and a high level is set at the alarm 21 output of the faulty block.

On the falling edge of the pulse from the decoder 4, the trigger 3 changes its state

0 to the opposite (in this case, is set to one), preparing the device for operation in the read mode. The output signal of the decoder 4, the passage through the delay element 8 and the element OR 6, sets the counter 2 to the zero state. The high signal level at the direct output of the trigger 3, i.e. at the output resolution of the device readout 22, permits the information receiver to access

0 with requests for reading data, a low signal level at the inverse output of the trigger 3, i.e. at the device write enable output 19, prohibits the source of information from accessing the device with requests

5 to write.

Upon receiving the read enable signal, the information receiver analyzes the presence of a fault in the received device to interface the data block by the fault signal from the output 21 of the device. If the data block

received without error, the receiver reads data from the device. If the data block is received with a fault, the receiver sends to the device (at input 23) a reset signal, which causes the interface to be reset. The input of the failed block did not occur, the interface device is ready for operation in the recording mode. The device allows the receiver of information, if necessary (if any) to enter and bad blocks. In this case, the reading is done in the usual way, but at the end of the reading, a reset signal is output to the mating input 23.

In read mode, the device operates as follows.

When reading each information word, the request of the information receiver arrives at the read synchronization input 24 and, passing through the element OR 5, acts on the synchronization input of the memory 1 of the memory, which results in the word read at the information outputs 18 read from the memory 1 at the address formed at the outputs of counter 2. Modification of the contents of counter 2 is carried out on the falling edge of the pulses fed to the counting input of counter 2 from input 24 through the element OR 5. In reading mode, just like in recording mode, a search for the sign End of block is conducted. In this case, the output signal of memory block 1 is connected to the decoder 4 through multiplexer 9, at the control input of which there is a high signal level at the moment. When reading from memory block 1, the word containing the End of block attribute, trigger 3 and counter 2 are set to the zero state, i.e. the device is prepared for operation in the data recording mode.

The device uses triggers 3 and 11, which have a high-level input to the zero state and change their state to the opposite on the falling edge of the signal at the synchronous input. Part 25 uses part K155IE5 of the counter; in the second case, element K15 is a type K155TM2 trigger, having a zero input signal with a low level signal and recording information from the input on the leading edge of the sync pulse at input C.

Claims (1)

Claims of Invention A device for coupling the source and receiver of information according to the author. St. No. 1658160, characterized in that, in order to increase the reliability of the device, an additional trigger and a decoder, two AND elements, a comparison circuit and a register are entered into it, the information input of the register is connected to the information input of the device, the first and second information inputs of the comparison circuit are connected respectively, with the outputs of the register and the counter, the synchronous input of the register is connected to the output of the first element I, the first input of which is connected to the synchronization input of the recording device, the second input - to the output of the additional an encoder connected to the output of the counter, the output of the initial installation of an additional trigger are connected to the alarm output of the failed device block and the device reset input, the output and the clock input of the comparison circuit are connected respectively to the synchronous input of the additional trigger and the output of the second element I, the first and second inputs connected to inverse trigger output and decoder output. 2 L. 27 Fig.Z If 23