JPS58105474A - Storage device - Google Patents

Abstract

PURPOSE:To eliminate a danger which may destruct the stored data and at the same time to simplify the peripheral system of an RAM, by writing the data of the rise or fall time point of the writing control signal into a memory cell of the RAM at an address at that moment. CONSTITUTION:A tristate buffer 5 is turned off (a high impedance state) and a writing driver 14 is driven (a low impedance state) in case the chip selection signal CS and the write enable signal WE are set at L. Then an input data is written to a memory cell which is selected with the column/row selection signal that is decoded and delivered from an address decoder 13. The driver 14 is turned off in case the signal CS and the signal WE are set at L and H respectively. Thus the driver 14 is not driven and the buffer 5 becomes enable, and the storage data which is sensed by a sense amplifier 15 is read out to an I/Oi terminal. Both the reading and writing are inhibited when the signal CS is set at H. IN such a way, the data of that moment is written to the address of the writing timing. As a result, the storage data is never destructed even through both signals S and WE are set at L at a time point before the addresses are switched.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a random access memory, and more particularly to a memory with improved write control signal (WIC signal) functionality.

Originally, in a writable memory, it is necessary to reliably write desired data to a desired address without disturbing several stored data at the same time.

The intersection of conventional memo IJ (RAM) will be explained. FIG. 1 is a time chart of input signals when continuous data is written into the memory almost in synchronization with address updating.

In response to changes in address and data, fl (write enable signal, active low) is allowed to go to the L# (low logic level) level only in the interval where the address and data are completely stable. At time ta, the WI double signal goes to L#, and the memory cell at address DD2 goes to DA.
The data of TM2 is driven. This continues until tb, at which point the drive runs out, and DmuTmu2 becomes MuDD2.
It will be written to the address. If the falling position of this 0 signal is before address/data switching time t1, Wl' becomes -L at 0 time tc considering wx-+wr, and DAT mu1 is placed at address DD7. Driven. Now, the address and data begin to change from time t1, but each bit of the address and data do not transition at exactly the same time, and of course there is a time difference between the address and data. Therefore, as can be easily imagined, some of the already stored data will be destroyed near time t1, which is very inconvenient. In actual continuous data writing, tc is often synchronized with tl (tb is located half way between tl and t2) to simplify the hardware. This usage makes the data stored in memory extremely unreliable.

The present invention has been made to eliminate these drawbacks and provide a memory that is extremely easy to use and requires simple peripheral hardware. This realizes a memory having a function of writing data at a falling point into a memory cell at the address at that time.

FIG. 2 shows an embodiment of the present invention. This embodiment is an example of a RAM with common input and output and a 10-bit address. 1 to 4 are data, address, O8 (chip select), respectively.
This is a WE (write enable) buffer. 6
is a tri-state buffer for data output. 6
10 are various gates, 9 forms a delay circuit for producing a predetermined delay time, and is an odd number of inverters. 11 and 12 are D latches for temporarily storing addresses and input data, respectively. 13 is an address decoder for selecting a memory cell corresponding to an address. 14 is a tri-state write driver, and 15 is a sense amplifier. 16 is a memory cell, 17 is a column switch, and 18 is a pull-up element.

Components other than 6 to 12 in FIG. 2 are the same as the conventional memory configuration, but the general operation will be briefly explained.

When chip select signal O8 is ``L'' and write
When the enable signal WR is "L", the tri-state buffer 5 is turned off (high impedance state), the write driver 14 is turned into a drive state (low impedance), and the address decoder 13 decodes and outputs the signal. The input data is written into the memory cell selected by the column and row selection signal. At CS="L",
When WE=°“H”, the write driver 14 is turned off and enters a non-drive state, the tri-state buffer 5 is enabled, and the stored data sensed by the sense amplifier 15 is read to the l10i terminal. O8-”
When it is H'', neither reading nor writing is possible.

FIG. 3 shows a timing diagram of each signal for explaining the present invention in detail. This is an operation in which M9 to M0, l10i, and C8°WE are input, and IIAT M1 is written to address MDD1. As is well known, RAM with O8 and WX
There are two timings to write data to: when the level changes to "H".

In the case of FIG. 3, it is the latter case, and C8 changes from L''' to 'H' at time t0, and the input data ( D
This is the case when writing ATM 1). (IL) in Figure 3~
(h) shows the output signals a to h of each gate in FIG. The signal e, which is activated by @LH→゛'H# of C8 when the time is off, and performs enable control of the D latch 11 and 12 and disable control of the write driver 14, has a width corresponding to the delay time of the delay circuit 9. A pulse of Tw is generated at time t1. D latches 11 and 12 latch the input signal at time 11 and temporarily store it until time t2. At the same time, the write driver 14 is enabled only from time t1 to t2 (TV) and performs a write drive operation. In practice, this time can be realized in several tens of nanoseconds or less.

In this way, the data at that time is written to the address at the write timing (WOE "L" → "H#" or aS "L# → "H71, etc.), so the address Even if the state becomes 03=lljii="L" at a time tb before the time ta when ta is switched, there is absolutely no fear that the stored data will be destroyed. Therefore, there is no restriction on the falling point of C-8 or 1x with respect to the address or data switching point, and it may fall at any point. Therefore, the system configuration of the logic circuits around the memory is correspondingly simplified.

In addition, change the writing timing from C8 L" to ゛H"H"
At no time, wx's "L" → "H#(CS,, = "L"
) It is easy to write only the address and data at the time. This way (flW-E's L"→"H'"
It is only necessary to control the point in time.

As explained above, according to the present invention, the write control signal such as WIC is active, active,
Since it is possible to obtain a RAM that can be written only at the position of the non-active edge (such as "L" → "1H"), and there is no restriction on the position of the non-active edge (such as "H" → "L#" of WR),
There is no risk of destroying the memory data, and the peripheral system for the memory is simple, making it highly effective.

[Brief explanation of the drawing]

Figure 1 is a diagram to explain the drawbacks of conventional memory, Figure 2 is a diagram to explain the drawbacks of conventional memory.
The figure is a specific circuit configuration diagram of an embodiment of the present invention, and FIG.
~ (hl is the signal waveform diagram of each part in Fig. 2. 9... Delay circuit, 11.12... D latch, 14... Write driver. Agent's Name Patent attorney Toshio Nakao and 1 other person 3rd
Figure Procedure Amendment (Knowledge April 12, 1988 Mr. Commissioner of the Japan Patent Office l Incident 1988 Patent Application No. 203937 2 Name storage device of invention 3 Person making the amendment 1'1 Relationship with Patent Issuance wish
Address: 1006 Kadoma, Kadoma City, Osaka Prefecture
Name (582) Matsushita Electric Industrial Co., Ltd. Representative Toshihiko Yamashita 4 Agent 571 Address 1006 Oaza Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. Date of 6 Amendment Order 7, Contents of Amendment (1) No. Correct Figure 3 as shown in the attached sheet. (2) Delete "(a) to (h)" on page 8, line 6 of the statement.

Claims (2)

[Claims] (1) A plurality of storage elements, a writing means for writing data to the storage elements, a reading means for reading the storage contents of the storage elements, and a write control signal is input to control the writing means. write control means for writing input data at a rising or falling point of the write control signal into a storage element corresponding to an address at the time. (2) The write control means includes a latch circuit that latches the input data and address for a predetermined period of time from the rise or fall of the write control signal. The storage device described in .