KR100522258B1 - Column select control circuit in synchronous semiconductor memory device and column select signal drving method - Google Patents

Abstract

A column selection control circuit and a column selection signal driving method of a synchronous semiconductor memory device are disclosed. The column selection control circuit of the present invention is a reference clock generating means for generating a read / write clock signal in response to an external clock signal, wherein the read / write clock signal is activated with a pulse having a predetermined width in response to the activation of the external clock signal. Reference clock generating means; And an enable signal generation means for generating a column select enable signal for enabling the column selector, wherein the column select enable signal is activated in response to the deactivation of the read / write clock signal, and the activation of the read / write clock signal. And said enable signal generating means which are deactivated in response. According to the column selection control circuit and the column selection signal driving method of the present invention, the pulse type signal generated by the activation of the external clock signal is inverted and provided as a column selection signal. Therefore, the column selection control circuit and its driving method of the present invention generate a column select enable signal that responds to the external clock signal with the same delay time for the external clock signal regardless of the CAS latency information. As a result, according to the column selection control circuit and the column selection signal driving method of the present invention, the configuration is simple and the control is easy.

Description

COLUMN SELECT CONTROL CIRCUIT IN SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND COLUMN SELECT SIGNAL DRVING METHOD}

The present invention relates to a synchronous semiconductor memory device and a driving method, and more particularly, to a column selection control circuit and a column selection signal driving method of a synchronous semiconductor memory device.

The synchronous semiconductor memory device is a semiconductor memory device that performs input / output operations of data in synchronization with an external clock signal provided from an external system. In general, a synchronous semiconductor memory device includes a memory array that is a collection of memory cells for storing data and peripheral circuits for controlling input and output of data stored in the memory array. The memory cells are arranged on a matrix formed of a plurality of word lines specifying a row of the memory array and a plurality of bit line pairs specifying a column. The bit line pairs are selected by activation of a column select signal provided from a column decoder. The column decoder is enabled in synchronization with a predetermined enable signal in response to the external clock signal, and also decodes a column address input in response to the external clock signal to generate the column selection signal. Therefore, it is very important to coincide with the activation timing of the enable clock signal and the timing when the column address is input to the column decoder.

FIG. 1 is a diagram illustrating a path for generating a column selection signal by decoding a column address and a control thereof in a conventional synchronous semiconductor memory device. Referring to FIG. 1, the column address YADD provided from the outside is input to the internal column address CA through the column address buffer 101 enabled in response to the external clock signal CLK. The internal column address CA is decoded by the column decoder 103, and the decoded column address DCA designates a column selection signal CSL that is activated through the column selection circuit 105. In FIG. 1, the column select circuit 105 is driven in response to the enable clock signal CLKC provided from the column select control circuit 107.

By the way, the column selection control circuit 107 of the conventional synchronous semiconductor memory device generates the enable clock signal CLKC by delaying the external clock signal CLK. The delay time of the external clock signal CLK is changed depending on the CAS latency CL, that is, the operating frequency of the synchronous semiconductor memory device. Therefore, the column selection control circuit of the conventional synchronous semiconductor memory device includes separate circuits for adjusting the delay time of the external clock signal CLK in response to the CAS latency information CL. Therefore, the column selection control circuit of the conventional synchronous semiconductor memory device has a problem in that its configuration is complicated and its control is difficult.

Accordingly, an object of the present invention is to provide a column selection control circuit and a column selection signal driving method of which the configuration is simple and easy to control.

One aspect of the present invention for achieving the above technical problem relates to a column selection control circuit of a synchronous semiconductor memory device. A synchronous semiconductor memory device including the column selection control circuit of the present invention is a memory array having a plurality of memory cells synchronized with a predetermined external clock signal and arranged on a matrix structure of rows and columns, and for selecting a row of the memory array. A row selector for generating a row select signal and a column selector for generating a column select signal for selecting a column of the memory array. The column selection control circuit of the present invention is a reference clock generating means for generating a predetermined read / write clock signal in response to the external clock signal, wherein the read / write clock signal has a predetermined width in response to activation of the external clock signal. The reference clock generating means for activating with a pulse of; And an enable signal generation means for generating a column select enable signal for enabling the column selector, wherein the column select enable signal is activated in response to the deactivation of the read / write clock signal and the read / write clock signal. And said enable signal generating means deactivated in response to the activation of.

One aspect of the present invention for achieving the above technical problem relates to a method of driving a column selection signal of a synchronous semiconductor memory device. The synchronous semiconductor memory device also has a memory array and a column selector as in the synchronous semiconductor memory device including the column selection control circuit. In the method of driving a column selection signal of a synchronous semiconductor memory device of the present invention, A) generating a predetermined read / write clock signal in response to the external clock signal, wherein the read / write clock signal is activated of the external clock signal. Generating a read / write clock signal that is activated in response to a pulse of a predetermined width in response; B) generating the column select enable signal activated in response to deactivation of the read / write clock signal and deactivated in response to activation of the read / write clock signal; And C) in response to the column select enable signal, activating the column select signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

2 is a block diagram conceptually illustrating a column selection control circuit 200 and a synchronous semiconductor memory device including the same according to an embodiment of the present invention. Referring to FIG. 2, a synchronous semiconductor memory device includes a memory array 100, a row selector 300, a column selector 400, and a column select control circuit 200 of the present invention.

The synchronous semiconductor memory device is synchronized with an external clock signal CLK provided from an external system. The memory array 100 includes a plurality of memory cells (not shown) arranged on a matrix structure consisting of rows ROW and columns COLUMN. Each of the memory cells may store data. Rows of the memory array 100 may be selected by activation of word lines (not shown), and columns of the memory array 100 may be selected by selection of bit line pairs (not shown). In addition, the word line and bit line pairs are selected and activated by a row select signal WDR and a column select signal CSL, which are designated by row addresses and column addresses, respectively.

The row selector 300 includes a row address buffer 310 and a row decoder 320. The row address buffer 310 is synchronized with the master clock signal CLKM which is activated in a predetermined width in synchronization with the external clock signal CLK. The row address buffer 310 buffers the row address XADD provided from an external system to thereby internal row address. Occurs with (RA). The row decoder 320 decodes the internal row address RA to provide a row selection signal WDR. The row selection signal WDR ultimately serves as information for selecting a row of the memory array 100. In the present embodiment, the row enable signal ROWEN is a signal generated by a row address strobe (/ RAS, not shown), etc., input from the outside, to enable circuits for specifying a row address. Signal to control.

The column selector 400 includes a column address buffer 410, a column decoder 450, and a column select circuit 470. The column address buffer 410 buffers a column address YADD provided from an external system in synchronization with the master clock signal CLKM to generate an internal column address CA (see t1 in FIG. 7). In the present embodiment, the column address YADD is composed of eight column addresses YADD0-7. The reference numerals of the column address (YADD), the internal column address (CA), the decoding column address (DCA), and the column selection signal (CSL), which are not appended with numerals, refer to the whole, and are attached. The number refers to a specific address number. For example, YADD7 refers to seven column addresses. In addition, DCA01 represents a decoding column address decoded by an internal column address CA0 of 0 and an internal column address CA1 of 0, and DCA234 represents an internal column address CA2 of 2 and an internal column address CA3 of 3. And a decoding column address decoded by four internal column addresses CA4.

 The column decoder 450 is a circuit for generating a decoding column address (DCA) which decodes the internal column address (CA), which is a 4: 1 decoding means 460 and two 8: 1 decoding means 465 and 467. ).

The 4: 1 decoding means 460 is enabled in response to a predetermined column select enable signal CSLEN, and decodes the internal column addresses CA0 and CA1 to provide a decoding column address DCA01. 3 illustrates the 4: 1 decoding means 460 in detail. Referring to FIG. 3, the 4: 1 decoding means 460 decodes CA0 and CA1 when the column select enable signal CSLEN is activated "high" (see t2 in FIG. 7). That is, by combining the logic states of CA0 and CA1, one of the decoding column addresses DCA01 <0> to DCA01 <3> is activated "high".

For example, if the logical states of CA0 and CA1 are both "high", DCA01 <0> is activated as "high", and if the logical states of CA0 and CA1 are both "low", DCA01 <3> is "high", High ". On the other hand, when the column select enable signal CSLEN is inactive to " low &quot;, the 4: 1 decoding means 460 does not decode the CA0 and CA1. That is, regardless of the logical state of CA0 and CA1, all of DCA01 <0> -DCA01 <3> are "low".

In the present specification and drawings, reference numerals < > added to the decoding column addresses are for distinguishing the decoding column addresses DCA provided from the same decoding means. For example, DCA01 <0> represents the decoding column address 0 provided from 4: 1 decoding means 460.

Referring again to FIG. 2, the 8: 1 decoder 465 decodes internal column addresses CA2 ˜ 4 to generate a decoding column address DCA234. The 8: 1 decoder 467 decodes internal column addresses CA5 to 7 to generate a decoding column address DCCA567. Since the 8: 1 decoders 465 and 567 can be easily implemented by those skilled in the art, the detailed description thereof is omitted.

The column selection circuit 470 is a circuit for decoding the decoding column address (DCA) and includes a plurality of column selection means 480. 4 is a diagram specifically showing one of the column selecting means 480 included in the column selecting circuit 470.

The column selecting means 480 shown in FIG. 4 is selected by predetermined signals DCA234 <i> and DCA567 <j> (where i and j are any one of 0 to 7). It is enabled when DCA567 <j> is all activated "high". In this specification, the DCA234 <i> denotes the decoding column address i provided from the 8: 1 decoding means 465 (see FIG. 2), and the DCA567 <j> denotes the 8: 1 decoding means 467 (see FIG. 2). Decoding column address provided from

The column select signals CSL <0> to CSL <3> output from the column selector 480 are activated in response to the decoded column signals DCA01 <0> to DCCA01 <3>. For example, when the decoding column signal DCA01 <0> is activated, the column selection signal CSL <0> is activated. In addition, when the decoding column signal DCA01 <3> is activated, the column selection signal CSL <3> is activated.

Referring back to FIG. 2, the read / write enable means 500 is enabled by the row enable signal ROWEN and the read / write enable signal RWEN in response to the read / write command signal RWCMD. Create In the present embodiment, the row enable signal ROWEN is a signal generated by a row address strobe (/ RAS, not shown), etc., input from the outside, to enable circuits for specifying a row address. Signal to control. The read / write enable signal RWEN tracks the read / write command signal RWCMD generated when the row enable signal ROWEN is activated to be “high”.

The column selection control circuit 200 of the present invention includes a reference clock generating means 600 and an enable signal generating means 700. FIG. 5 is a diagram illustrating in detail the reference clock generating means 600 of FIG. 2.

The reference clock generating means 600 is enabled in response to a predetermined clock enable signal CKE and a row enable signal ROWEN, and has a predetermined pulse width in response to activation of the external clock signal CLK. The activating master clock signal CLKM and the read / write clock signal CLKRW are generated (see t3 in FIG. 7). The read / write clock signal CLKRW has an activation duty of less than 50%.

Specifically, the reference clock generating means 600 includes a delay unit 611, an inverter 613, and first and second logic gates 615 and 617.

The delay unit 611 delays the clock external signal CLK by a predetermined time. The inverter 613 inverts the output signal N612 of the delay unit 611. The first logic gate 615 performs an AND operation on the external clock signal CLK, the output signal N614 of the inverter 613, and the clock enable signal CKE. The output signal N616 of the first logic gate 615 passes the buffer unit 619 to generate the master clock signal CLKM. The clock enable signal CKE is a signal for controlling the synchronous semiconductor memory device of the present invention to enter a state capable of receiving an external clock signal CLK, and is activated as “high” in the present specification.

The second logic gate 617 performs an AND operation on the output signal N616, the row enable signal ROWEN, and the external clock signal CLK of the first logic gate 615. Accordingly, the read / write clock signal CLKRW, which is an output signal of the second logic gate 617, responds to the external clock signal CLK when the row enable signal ROWEN is activated as “high”. do.

FIG. 6 is a diagram illustrating the enable signal generating unit 700 of FIG. 2 in detail. The enable signal generating means 700 is enabled in response to the read / write enable signal RWEN and provides the column select enable signal CSLEN in response to the read / write clock signal CLKRW. do. Specifically, the column enable generating means 700 includes third and fourth logic gates 751 and 753.

The third logic gate 751 logically multiplies the column block selection signal SCA by the column enable signal YEN. The column block selection signal SCA is a signal for selecting a block including a column address of a selected bit line pair, and is referred to herein as "high". The column enable signal YEN is a circuit for enabling peripheral circuits for designating a column address and is activated after a predetermined time tRCD has elapsed from the activation of the row enable signal ROWEN. . In this specification, the read / write enable signal RWEN is already activated “high” before being activated.

The fourth logic gate 753 is the inverted signal N756 of the output signal N552, the read / write enable signal RWEN and the read / write clock signal CLKRW of the third logic gate 751. Perform an AND operation. Accordingly, the read / write clock of the column select enable signal CSLEN, which is an output signal of the fourth logic gate 753, is activated while the read / write enable signal RWEN is activated to be “high”. Respond to signal CLKRW. In other words, when the read / write clock signal CLKRW is activated to "H", the column select enable signal CSLEN is deactivated to "L", and the read / write clock signal CLKRW is set to "L". When, the column select enable signal CSLEN is activated to " H ". In summary, as in the present embodiment, the column select enable signal CSLEN is the read / write enable signal ( RWEN) is activated by " high ", generated by inversion of the read / write clock signal CLKRW. That is, the column select enable signal CSLEN is activated as "H" after a predetermined time elapses from the activation of the external clock signal CLK, and then by the activation of the next external clock signal CLK. Is disabled. In this case, the column select enable signal CSLEN is inactivated during the activation period of the read / write clock signal CLKRW. The read / write clock signal CLKRW has an activation duty of 50% or less as described above. As a result, the column select enable signal CSLEN responds to the read / write clock signal CLKRW. In this case, the read / write clock signal CLKRW is activated in response to the external clock signal CLK. Accordingly, the column select enable signal CSLEN is a result of responding to the external clock signal CLK. That is, the column select control circuit of the present invention is fixed in response to the clock of the external clock signal CLK. A column select enable signal CSLEN is generated that is activated during the interval. At this time, the activation of the column select enable signal CSLEN is irrelevant to CAS latency.

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In conclusion, according to the column selection control circuit of the present invention, separate circuits for changing the delay time according to CAS latency information as in the prior art are not required, and the column selection enable is synchronized with the external clock signal CLK. The signal CSLEN is generated. Therefore, the column selection control circuit of the present invention is simple in configuration and easy to control.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the column selection control circuit and the column selection signal driving method of the present invention as described above, the pulse type signal generated by the activation of the external clock signal is inverted and provided as a column selection signal. Therefore, the column selection control circuit and its driving method of the present invention have the same delay time for the external clock signal regardless of the CAS latency information, and automatically selects a column selection enable signal (synchronized to the external clock signal CLK). CSLEN). As a result, according to the column selection control circuit and the column selection signal driving method of the present invention, the configuration is simple and the control is easy.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

FIG. 1 is a diagram illustrating a path for generating a column selection signal by decoding a column address in a conventional synchronous semiconductor memory device and a control thereof.

2 is a block diagram conceptually illustrating a column selection control circuit and a synchronous semiconductor memory device including the same according to an embodiment of the present invention.

3 is a diagram specifically showing a 4: 1 decoding means.

4 is a diagram specifically showing one of the column selection means included in the column selection circuit.

FIG. 5 is a diagram illustrating in detail the reference clock generating means of FIG. 2.

FIG. 6 is a diagram illustrating in detail the enable signal generating unit of FIG. 2.

7 is a timing diagram of a main signal for explaining a process of a column selection signal in the synchronous semiconductor memory device including the column selection control circuit of the present invention.

Claims (6)

A memory array having a plurality of memory cells arranged in a matrix structure of rows and columns, synchronized with a predetermined external clock signal, a row selector for generating a row select signal for selecting a row of the memory array, and a column of the memory array In the column selection control circuit of a synchronous semiconductor memory device comprising a column selection unit for generating a column selection signal for selecting a, A reference clock generating means for generating a predetermined read / write clock signal in response to the external clock signal, wherein the read / write clock signal is activated with a pulse having a predetermined width in response to the activation of the external clock signal; Generating means; And Means for generating a column select enable signal for enabling the column selector, wherein the column select enable signal is activated in response to deactivation of the read / write clock signal, and And said enable signal generating means deactivated in response to activation. The method of claim 1, wherein the enable signal generating means During the deactivation of the row selection signal, in order to block activation of the column selection signal, the row selection signal is enabled in response to activation of a read / write enable signal activated by a read / write command input to the synchronous semiconductor memory device. A column selection control circuit of a synchronous semiconductor memory device. The method of claim 2, wherein the reference clock generating means And enable in response to activation of a row enable signal for enabling the row selector. The method of claim 3, wherein the reference clock generating means And a logic gate that performs an AND operation on the row enable signal, the external clock signal, and a delay signal of the external clock signal. The method of claim 2, wherein the enable signal generating means And a logic gate that performs an AND operation on the read / write enable signal and the inverted signal of the access reference clock signal. A method of driving a column selection signal of a synchronous semiconductor memory device synchronized with a predetermined external clock signal, comprising: a memory array having a plurality of memory cells arranged on a matrix structure of rows and columns, and a column selection signal for selecting a column of the memory array; The column selector that is generated in response to a predetermined column select enable signal, wherein the column selector inputs a column address for selecting a column of the memory array in synchronization with the external clock signal; In the column selection signal driving method of the synchronous semiconductor memory device having a unit, A) generating a predetermined read / write clock signal in response to the external clock signal, wherein the read / write clock signal is activated by a pulse having a predetermined width in response to the activation of the external clock signal. Generating a clock signal; B) generating the column select enable signal activated in response to deactivation of the read / write clock signal and deactivated in response to activation of the read / write clock signal; And C) activating the column select signal in response to the column select enable signal.