JPS5668989A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS5668989A
JPS5668989A JP14469379A JP14469379A JPS5668989A JP S5668989 A JPS5668989 A JP S5668989A JP 14469379 A JP14469379 A JP 14469379A JP 14469379 A JP14469379 A JP 14469379A JP S5668989 A JPS5668989 A JP S5668989A
Authority
JP
Japan
Prior art keywords
address
circuit
internal clock
generated
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14469379A
Other languages
Japanese (ja)
Other versions
JPS6221196B2 (en
Inventor
Yasuo Akatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14469379A priority Critical patent/JPS5668989A/en
Priority to US06/139,595 priority patent/US4337525A/en
Priority to EP80102068A priority patent/EP0017990B1/en
Priority to DE8080102068T priority patent/DE3070410D1/en
Publication of JPS5668989A publication Critical patent/JPS5668989A/en
Publication of JPS6221196B2 publication Critical patent/JPS6221196B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To prevent the malfunction to the noise, by giving an enable state to the block which is controlled by the internal clock generated by the logic variation of the address through the reset state after the logic variation of the address input. CONSTITUTION:The internal clock generating circuit D detects the logic variation of the address inputs A0-An via the delaying circuit and the exclusive OR circuit and then generates the internal clock CE to secure a synchronization among the memory cell array C, address decoder circuit DE, input/output buffer circuit IO and address buffer circuit B each. In this instant, the reset signal of the fixed time T2 is generated first through the logic change of the address input A0, and then the enable signal CE is generated. In such way, only the time duration of the reset signal extends to e.g. noise N. Thus the nonoperation state is given meanwhile to cause no malfunction.
JP14469379A 1979-04-17 1979-11-08 Memory circuit Granted JPS5668989A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP14469379A JPS5668989A (en) 1979-11-08 1979-11-08 Memory circuit
US06/139,595 US4337525A (en) 1979-04-17 1980-04-11 Asynchronous circuit responsive to changes in logic level
EP80102068A EP0017990B1 (en) 1979-04-17 1980-04-17 Integrated memory circuit
DE8080102068T DE3070410D1 (en) 1979-04-17 1980-04-17 Integrated memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14469379A JPS5668989A (en) 1979-11-08 1979-11-08 Memory circuit

Publications (2)

Publication Number Publication Date
JPS5668989A true JPS5668989A (en) 1981-06-09
JPS6221196B2 JPS6221196B2 (en) 1987-05-11

Family

ID=15368066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14469379A Granted JPS5668989A (en) 1979-04-17 1979-11-08 Memory circuit

Country Status (1)

Country Link
JP (1) JPS5668989A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59221891A (en) * 1983-05-31 1984-12-13 Toshiba Corp Static semiconductor storage device
JPS60182595A (en) * 1984-03-01 1985-09-18 Toshiba Corp Random access memory
JPS61220190A (en) * 1985-03-26 1986-09-30 Matsushita Electric Ind Co Ltd Data transmitting circuit
JPS62221747A (en) * 1986-03-19 1987-09-29 Fujitsu Ltd Semiconductor memory device
JPH0574162A (en) * 1991-09-20 1993-03-26 Toshiba Corp Static type semiconductor memory device
KR100425661B1 (en) * 1998-05-07 2004-04-03 가부시끼가이샤 도시바 Data synchronous transmitting system and method of synchronously transmitting data

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019225735A1 (en) 2018-05-25 2019-11-28 株式会社ＺｅｎｍｕＴｅｃｈ Data processing device, method, and computer program

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS=1977 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59221891A (en) * 1983-05-31 1984-12-13 Toshiba Corp Static semiconductor storage device
JPH0253879B2 (en) * 1983-05-31 1990-11-20 Tokyo Shibaura Electric Co
JPS60182595A (en) * 1984-03-01 1985-09-18 Toshiba Corp Random access memory
JPS61220190A (en) * 1985-03-26 1986-09-30 Matsushita Electric Ind Co Ltd Data transmitting circuit
JPS62221747A (en) * 1986-03-19 1987-09-29 Fujitsu Ltd Semiconductor memory device
JPH0568796B2 (en) * 1986-03-19 1993-09-29 Fujitsu Ltd
JPH0574162A (en) * 1991-09-20 1993-03-26 Toshiba Corp Static type semiconductor memory device
JP2580086B2 (en) * 1991-09-20 1997-02-12 株式会社東芝 Static semiconductor memory device
KR100425661B1 (en) * 1998-05-07 2004-04-03 가부시끼가이샤 도시바 Data synchronous transmitting system and method of synchronously transmitting data

Also Published As

Publication number Publication date
JPS6221196B2 (en) 1987-05-11

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