JPH0568796B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In the semiconductor memory device according to the present invention, when detecting that an address input signal selects a specific address, the semiconductor memory device according to the present invention detects that the address input signal selects a specific address until the selection period reaches a predetermined time interval. An address selection detection circuit is provided that does not consider an address to be selected. As a result, when switching from one address to another address, the switching timing of the address signal is slightly shifted for each bit, so that the specific address can be selected transiently. Even if such a transitional selection state occurs, it is possible to prevent the occurrence of such a transient selection state from being mistaken as a normal selection for the specific address.

[Industrial application field]

The present invention relates to a semiconductor memory device, and in particular, a plurality of CPUs are connected to the semiconductor memory device, and the memory device and the CPU
The present invention relates to a multi-port semiconductor memory device configured to transfer data between the CPU and output an interrupt signal to a predetermined CPU as necessary.

[Conventional technology]

In recent years, demands for higher performance systems have led to an increase in the number of systems incorporating multiple CPUs, and this has led to an increase in demand for so-called multi-port RAM. Figure 9 shows the so-called 2-port
This figure shows the schematic configuration of RAM, and shows a pair of left and right ports for a common memory cell array 11 (i.e., the right port (symbol R ) and the left port (marked with L), which consists of an address buffer 16, a row decoder 17, a column decoder 18, an I/O buffer 19, etc. The left and right ports each have a corresponding CPU
The CPUs are connected to each other and operate in response to instructions from the corresponding CPU. In this case, each CPU connected to the left and right ports usually operates independently and selects a predetermined address (determined by the levels of A ₀ R to AnR and A ₀ L to A _o L), and selects the specified address. Reading data from the memory cell corresponding to the selected address (D _OUT R and D _OUT
(denoted by L) and writing of data to the corresponding memory cells (denoted by D _IN R and D _IN L) is performed.

By the way, in such a multi-port RAM, the CPU connected to the multi-port RAM
Direct communication between
There is a device equipped with a so-called direct interaction control circuit 2' having a function. That is, for example, in a two-port RAM, when a CPU connected to the left port side communicates directly with a CPU connected to the right port side, as shown in Fig. 5, the RAM is A specific address (let's say address a) is selected (AL becomes a), and predetermined information is written to address a (during the write period, the write command signal L from the left port side becomes low level). ), the interrupt signal R is output to the right port side of the RAM (R becomes low level), and the CPU on the right port side that received the interrupt signal
At the point when performs a specific process (for example, reading information written to address a) (that is, AR becomes a and the write command signal R from the right port side becomes high level, that is, a read command),
The interrupt signal R is cleared (ie, at high level). Note that such direct interaction is performed in the same manner from the right port side to the left port side. (In this case, this is done via another specific address in the RAM, for example address b). Also in Figure 5
The shaded portion of WER indicates that it is at either a high level or a low level, and as described above, a low level corresponds to a write command and a high level corresponds to a read command.

FIG. 6 shows an example of the direct interaction control circuit 2' for performing such direct interaction, and FIG. A circuit for generating R is illustrated. In this figure, 22 is an exclusive OR circuit, 24 is an inverter, 23, 25, 26 and 27 are NOR gates, and the left port side is the corresponding one.
By selecting address a of the RAM and writing predetermined data into the address a (setting L to low level), an interrupt signal R is output from the output side of the NOR gate 27 to the right port side. Further, 21' is an address selection detection circuit that generates a signal for clearing (setting to high level) the interrupt signal R, 211 is an exclusive OR circuit, 212 is an inverter, and 213 is a NOR circuit. When it is determined that the right port side has selected the address a and is ready to read the data written to the address a from the left port side (R becomes high level), the interrupt signal R is sent. A signal to clear (set to high level) is output.

FIG. 7 is a timing diagram illustrating the operation of the circuit shown in FIG. 6 above. Now, in Figure 7, the left port side selects address a of the RAM (AL selects address a
), when writing predetermined data to the address a (L becomes low level), the output side of the exclusive OR circuit 22 becomes low level, and then the output side of the NOR gate 23 becomes high level, and during that time The output side of the NOR gate 25 becomes high level. In this way, the left port side selects address a of the RAM and writes predetermined data to address a, thereby controlling the NOR gate 27.
A low level interrupt signal R is output from the output side to the right port side.

As a result, the CPU connected to the right port immediately accepts the interrupt signal R, or
If the signal R is still not accepted due to timing, the interrupt signal
It receives INTR and performs read processing of the data written to the address a of the RAM.

In this way, when the right port side selects address a of the RAM (AR becomes a) and enters the mode of reading predetermined data from address a (R becomes high level), the interrupt Since reception of the signal R has ended, the output side of the exclusive OR circuit 211 in the interrupt clear signal generating circuit 21' is set to low level, the output side of the inverter 212 is also set to low level, and the output side of the NOR gate 213 is set to high level. Generates a level interrupt clear signal. As a result, Noah Gate 2
The output side of NOR gate 27 and the output side of NOR gate 26 both become low level, and the interrupt signal R outputted from the output side of NOR gate 27 becomes high level, thereby clearing the interrupt signal. In other words, it is determined that the CPU on the right port side has accepted the interrupt signal R output from the right port of the RAM and is now in a state to perform a predetermined process (in the above case, reading data from the address a). At the point when
The interrupt signal R will be cleared (reset).

[Problem that the invention seeks to solve]

However, in the circuit shown in FIG. 6 described above, even if the low level interrupt signal R is now output to the right port side,
Due to reasons such as the need to execute certain processing preferentially before the CPU on the right port side accesses the address a, the signal is not yet processed due to the timing.
INTR may not be accepted, and the previously selected address may be switched from address x to address y, which is different from address a. In such a case, especially in an asynchronous memory, the switching timing for each bit from the address x to y does not actually match exactly, but may deviate somewhat. That is, for example, as shown in FIG. 3, A ₀ R (“0” in this case), A ₁ R (“1” in this case), and A _o R (“1” in this case) that make up the address x are each constitutes the address y
The timings of switching to A ₀ R (“1” in this case), A ₁ R (“0” in this case), and A _o R (“0” in this case) are shifted from each other, and transient Generally, the selected address is address a (consisting of A ₀ R=1, A ₁ R=1, . . . A _o R=1) and address Z (A ₀ R=1, A ₁ R=0,
...consisting of A _o R=1).

Therefore, in the circuit shown in FIG. 6 above, when the right port side is in the read mode (R is high level), the interrupt signal R is immediately transmitted on the condition that the address a is selected. For example, as described above, the right port side
When the CPU selects the address a due to a transient phenomenon even though it has not actually accepted the interrupt signal R and read the data at the address a (see Figure 8A).
Also, when the level on the output side of the exclusive OR circuit 211 becomes low level, the level on the output side of the NOR gate 213 becomes high level, and the interrupt signal R is erroneously cleared. (See Figure 8A).

The present invention has been made to solve such problems, and the above-mentioned transient address selection may be mistaken as a regular address selection, and for example, the above-mentioned interrupt signal may be cleared by mistake. This prevents

[Means for solving problems]

According to the present invention, in order to solve the above problems,
Interrupt signal control means outputs an interrupt signal to a second port by writing to a certain address from the first port, and resets the interrupt signal by reading the certain address from the second port. a clear prevention signal that is output for a predetermined period of time when an address input signal supplied to the second port changes even if the second port reads the certain address; means for inhibiting the reset of the interrupt signal by φR until a selection period for detecting that the address input signal supplied to the second port has selected the certain address reaches a predetermined time interval; A multi-port memory is provided.

[Effect]

According to the above configuration, until the address selection period reaches a predetermined time interval, it is not considered to be a regular address selection, and for example, when predetermined data is written to the specific address via one port, the other Even if an interrupt signal is output to one port and the other port is in read mode,
Until the selection period of the specific address from the other port reaches a predetermined time interval, the specific address is not considered to have been selected (that is, the interrupt signal has been accepted), and the interrupt signal clearing (resetting) is prevented.

〔Example〕

FIG. 1 schematically shows the overall configuration of a multi-port memory circuit as a first embodiment of the present invention, and the multi-port memory circuit includes a direct interaction control circuit 2 configured as described below. It is provided.

That is, FIG. 2 shows one embodiment of the direct interaction control circuit 2 according to the present invention, and as in the case of FIG. 6 above, only the circuit that controls direct interaction from the left port side to the right port side is used. It is shown.

The difference between the circuit shown in FIG. 2 and the circuit shown in FIG. 6 is that the specific address (in this case A circuit 210 is provided which generates a signal φR that prevents the interrupt signal R from being cleared until the selection period of address a) reaches a predetermined time interval.

FIG. 4 shows the interrupt clear block signal generation circuit 210.
This shows a specific example of 2150 to 215n.
are exclusive OR circuits, and each of the circuits 2150 to 215n receives the address signals A ₀ R to AnR inputted from the right port side directly for each bit and to each of the delay circuits 2140 to 214n.
They are respectively input via n. Therefore, when switching the selected address, address input A ₀
When a level change occurs in R to AnR, during the delay time set by the delay circuits 2140 to 214n, the corresponding exclusive OR circuits 2150 to 2150 change due to the difference in the two input levels. The output of 215n becomes high level, and therefore the signal φR outputted from the OR circuit 216 to which the output is supplied also becomes high level.

That is, as shown in FIG. 3, even if there is a time lag in the level changes of the address inputs A ₀ R to AnR, from the time of the level change of A ₀ R, which changes the level first in FIG. The OR circuit 216 outputs a signal φR that is at a high level during the period leading up to the time when the level of AnR changes (more precisely, the time when a predetermined delay time has elapsed from the time of the change). Even if the right port side transiently selects the address a in the read mode (that is, the output side of the exclusive OR circuit 211 and the inverter 21
Even if the output sides of 2 are both low level),
The interrupt clear signal output from the NOR circuit 213 remains at low level, and the interrupt signal R
is prevented from being cleared by mistake.

FIG. 8B shows the above operation in comparison with the conventional example shown in FIG. 8A.
In this case, the interrupt clear signal output from the output side of the exclusive OR circuit 213 temporarily becomes high level due to the above-mentioned transient address selection (selection of address a in this case), and accordingly, However, in the circuit of the present invention, as shown in FIG. 8B, even if such a transient selection of the address a is made, the The output side of the circuit 213 remains at the low level due to the generation of the interrupt clear prevention signal φR which is at the high level for a predetermined time when the input changes, and therefore the output sides of the NOR circuits 25 and 26 are both at the high level. Therefore, the interrupt signal R output from the NOR circuit 27 is maintained at a low level, and the erroneous clearing is prevented.

Note that although FIG. 2 above shows a circuit that controls direct interaction from the left port side to the right port side, a circuit that similarly controls direct interaction from the right port side to the left port side is also shown. It is obvious that it can be configured, and in this case, when detecting that the left port side has selected a specific address (for example, address b), the selection period will be delayed until the selection period reaches a predetermined time interval corresponding to the delay time described above. is interrupt signal L
It is clear that the structure can be configured to prevent the clearing of the data.

〔Effect of the invention〕

According to the present invention, when a specific address is temporarily selected even though no access is actually made to the specific address, the specific address remains legal until the selection period reaches a predetermined time interval. This ensures that, for example, it is not possible to accidentally clear a desired interrupt signal before accepting it.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of a multiport memory circuit as an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing one embodiment of the direct interaction control circuit in FIG. 1, FIG. 3 is a timing diagram explaining the operation of FIG. 2, and FIG. FIG. 5 is a circuit diagram illustrating a specific example; FIG. 5 is a timing diagram illustrating the general operation of a direct interaction control circuit in the prior art; FIG. 6 is a circuit diagram illustrating a direct interaction control circuit in the prior art; FIG. is a timing diagram explaining the operation of FIG. 6, and FIG.
The figure is a timing diagram showing a comparison of the operations of the circuit of the present invention and the circuit of the prior art, and FIG. 9 is a diagram showing the overall configuration of the multiport memory circuit of the prior art. Explanation of symbols, 2, 2'...direct interaction control circuit,
21, 21'...Address selection detection circuit (interrupt clear signal generation circuit), 210...Interrupt clear blocking signal generation circuit, 2140,...214n...Delay circuit.

Claims (1)

[Claims] 1. Interrupt signal control means that outputs an interrupt signal to a second port by writing to a certain address from the first port, and resets the interrupt signal by reading the certain address from the second port. a multi-port memory having a clear block which is output for a predetermined time even if the second port reads the certain address, when the address input signal supplied to the second port changes; The interrupt signal is reset by the signal (φR) until the selection period for detecting that the address input signal supplied to the second port has selected the certain address reaches a predetermined time interval. A multi-port memory characterized by being provided with a means for prohibiting.