JPS5558893A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS5558893A
JPS5558893A JP12286979A JP12286979A JPS5558893A JP S5558893 A JPS5558893 A JP S5558893A JP 12286979 A JP12286979 A JP 12286979A JP 12286979 A JP12286979 A JP 12286979A JP S5558893 A JPS5558893 A JP S5558893A
Authority
JP
Japan
Prior art keywords
memory
high level
timing
precharge
content
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12286979A
Other languages
Japanese (ja)
Other versions
JPS597159B2 (en
Inventor
Shigeki Matsue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP54122869A priority Critical patent/JPS597159B2/en
Publication of JPS5558893A publication Critical patent/JPS5558893A/en
Publication of JPS597159B2 publication Critical patent/JPS597159B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To intermit the refresh of dynamic memory without injuring the memory content, by enabling the precharge operation only when the address lines are all at low level. CONSTITUTION:When one of the write in address lines AL2, AL2'... is at high level and when either memory is refreshed, either of the gates Q11, Q12... is conductive, and the precharge timing signal P2 is not high level with the high level of inversion signal in the timing signal and the digit lines are not precharged. Accordingly, even if the refresh cycle is intermittent with any timing, the memory content of the memory in matrix formation is not changed, and the dynamic memory requiring precharge is controlled in the good timing not disturbing the content of memory cell. Further, the similar result can be obtained, by delaying the period of high level timing signal when the digit lines are inverted to high or low level by using a delay circuit.
JP54122869A 1979-09-25 1979-09-25 memory circuit Expired JPS597159B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54122869A JPS597159B2 (en) 1979-09-25 1979-09-25 memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54122869A JPS597159B2 (en) 1979-09-25 1979-09-25 memory circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9437072A Division JPS568435B2 (en) 1972-09-19 1972-09-19

Publications (2)

Publication Number Publication Date
JPS5558893A true JPS5558893A (en) 1980-05-01
JPS597159B2 JPS597159B2 (en) 1984-02-16

Family

ID=14846640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54122869A Expired JPS597159B2 (en) 1979-09-25 1979-09-25 memory circuit

Country Status (1)

Country Link
JP (1) JPS597159B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63247997A (en) * 1987-04-01 1988-10-14 Mitsubishi Electric Corp Semiconductor storage device
US5504438A (en) * 1991-09-10 1996-04-02 Photon Dynamics, Inc. Testing method for imaging defects in a liquid crystal display substrate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61146264U (en) * 1985-03-04 1986-09-09

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63247997A (en) * 1987-04-01 1988-10-14 Mitsubishi Electric Corp Semiconductor storage device
US5504438A (en) * 1991-09-10 1996-04-02 Photon Dynamics, Inc. Testing method for imaging defects in a liquid crystal display substrate

Also Published As

Publication number Publication date
JPS597159B2 (en) 1984-02-16

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