JPS6257048A - Decentralized processor system - Google Patents

Abstract

PURPOSE:To judge from which processor a parity error is detected even when bus contention exists when the parity error is detected in a data fetched from a bus by providing an enable signal generating circuit or the like. CONSTITUTION:A microinstruction outputting the output of an arithmetic unit section 27 is executed by processors 11, 13 due to malfunction of a system, processors 12, 14 apply an instruction storing a data on a bus in a data input register 21, then bus contention is caused. Thus, a data parity error is detected and an enable signal generation circuit 24 of the processors 11, 13 supplies a signal (a) enabling a bus driver 23 to the driver 23 and an enable signal hold circuit 25. Further, the signal (a) is transferred to a main storage 10 via a bus 15, an area represented by an address limited at each processor storage in the main storage 10 is read sequentially to check the level of the signal (a). Thus, from which processor the parity error is sent is judged and from which inter-processors the error comes is recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a distributed processor system having a plurality of bus-connected processors that operate synchronously.

[Conventional technology]

In recent years, systems with bus configurations in which many processors are connected to a data bus and exchange data have been widely implemented.In order to maintain the reliability of data on the bus, parity is added and the data is It is common practice to perform a yari tee check when entering the game.

[Problem that the invention seeks to solve]

However, in a system with a bus configuration, data A9.
If a bus error is detected, it is difficult to immediately and easily determine which processor sent the data even if there is no bus contention, or if a system malfunction has caused a bus usage conflict. This has the drawback that in the event that the data becomes invalid or an error occurs, it becomes even more difficult to identify the processor to which the data is sent.

The purpose of the present invention is to use simple hardware to determine which processor has sent the data, even if an error is detected in the data received from the bus or if there is bus contention. The goal is to provide the following.

[Means for solving problems]

A distributed processor system according to the present invention is a distributed system in which a main memory and a plurality of microprogram-controlled processors are connected by a bus.

Each of the processors has a data input register H connected to the bus, an enable signal generation circuit that generates an enable signal under the control of a microprogram, and when the enable signal is input, the internal data of the processor is transferred to the node Z. It is rumored that the bus driver has a function to send data to the bus, or it inputs the contents of the bus to the data input register, or it sends the data to the bus.
A data bus check circuit that checks the EIJ property and holds the result, and the enable signal and the output signal of the data bus check circuit are input, and when a data error on the bus is detected, the enable signal If the enable signal holding circuit that holds the signal and the data bus check circuit detect an error and the enable signal is held, when the processor is on the sending side, the data on the main memory connected to the bus is The present invention is characterized by comprising means for storing the state of the enable signal holding circuit, which is error information, in the area.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

This system consists of a main memory 10 and a processor 11゜12.1
3.14 are connected by a bus 15 to form a plurality of processors. Each processor is a microprogram controlled processor and operates synchronously. Inside each processor, although only 11 is shown in Figure 9, there is a data input register 21 connected to the bus 15, and when data is sent to the bus 15 or data is taken into the data input register 21, the data input register 21 is connected to the bus 15. and a data bus check circuit 22 that checks and checks data and holds the results.

Bus driver/6-2 for sending data to bus 15
3, the enable signal generation circuit 24 that generates the enable signal a of this bus driver, and the output of the data bus check circuit 22. If the output is 10, the enable signal a is not held; An enable signal holding circuit 25 that holds the enable signal a, a microprogram control section 26, and the microprogram control section 2
It has an arithmetic unit 27 which receives the output of the data input register 21 and the output C of the enable signal holding circuit 25 under the control of the data input register 6, and performs various data processing and holding.

FIG. 2 shows a time chart when a data transfer from the processor 11 to the processor 12 and a data transfer from the processor 13 to the processor 14 conflict, resulting in invalid data and a data parity error. In the diagram showing the operations of 11 to 14.

A, B, and C indicate microinstructions of each processor.

A is a microinstruction that sends internal data to the bus 15 in order to transfer data to another processor, C is an instruction to take the data on the bus 15 into the data input register 21, and B is an enable signal holding circuit because a data error has been detected. If the output C of the enable signal holding circuit 25 is "1#," then the error processing is activated in the micro zorogram, indicating a command to store the state of the enable signal holding circuit 25, that is, error information at a specific address in the main memory 10. ing.

Based on the above, this embodiment will be described in detail. Due to system malfunction, processors 11 and 13
Executes a microinstruction that outputs the output of f to bus 15,
Bus contention occurs when processors 12 and 14 execute an instruction to store data on the bus into data input register 21. The enable signal generation circuit 24 of the processors 11 and 13 outputs a signal a for enabling the bus driver 23 under the control of the microprogram control section 26, and supplies the signal a to the bus driver 23 and the enable signal holding circuit 25. When the enable signal a becomes "1", the bus driver 23 sends the output of the arithmetic unit 27 to the bus 15, but since the processes 11 and 13 are sending data at the same time,
The data on bus 15 becomes invalid. On the other hand, processors 12 and 14 take in data on the bus into data input register 21. Since the data bus check circuit 22 checks the bus data when it sends data to the bus 15 or receives data into the data input register 21, the processors 11 to 14 all detect invalid data on the bus 15. Detect and set output to “1”. In synchronization with this, the enable signal holding circuits 25 of the processors 11 and 13 hold the ul# of the output a of the enable signal generating circuit 24, and the enable signal holding circuits 25 of the processors 12 and 14 hold the output a of the enable signal generating circuit 24. °0”, so “O”
” is held. When the enable signal holding circuit 25 becomes “1”, the signal C is transmitted to the microprogram control unit 26 of the processors 11 and 13, and the f processors 11 and 1
3 executes microinstruction B, which is an error processing instruction. As a result, under the control of the microprogram control section 26, the calculation section 27 outputs an enable signal, and this output is sent to the bus 15 and transferred to the area indicated by the address specified for each processor in the main memory 10. be done.

The Shigure processors 11 and 13 make access requests to the main memory 10, but in the time chart, the processor 11 executes the data transfer to the main memory 10 first; Rather than showing what must be done.

The processor 13 may be the first to request access to the main memory 10, and the one that is accepted first transfers the data to the main memory 10.

Those who are not accepted will have to wait until then.

This control is not related to the present invention, so a detailed explanation will be omitted. Therefore, in order to analyze the cause of the error, if a bus data error is detected, the areas stored in the main memory 10 indicated by addresses limited to each processor are sequentially read out, and the enable signal a is "1". By checking whether the error occurred, you can find out which processor the error occurred between.

In the above, we have described the case where a data error occurs due to contention on the bus 15, but this is not the only case; when simply transferring data from one processor 11 to the other processor 12, the sending processor may receive invalid data. Needless to say, it is also effective when sent. The operation in this case is the same as described above, the difference being that the processor 13
．． There are only 14 movements. Further, in the present invention, the data input register 21 is not used when an error occurs.

This has the advantage that not only the contents held in the data input register are not destroyed, but also the data held in the arithmetic unit 27 does not need to be changed, so that the state of the processor is preserved. This facilitates restarting the system after error handling.

〔Effect of the invention〕

As explained above, according to one aspect of the present invention, in a distributed processor system, when invalid data is sent to the bus or when bus contention occurs, the processor to which the data is sent can read out the contents stored in the main memory. This has the effect that not only can a decision be made quickly, but also a system that can make a decision without destroying the contents of data stored in the processor when an error occurs can be realized with a small amount of hardware.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of a distributed processor system that is an embodiment of the present invention, and Fig. 2 is a diagram showing the time when a data/J/IJ error occurs due to data transfer conflict in the system shown in Fig. 1. It is a figure which shows a chart. Explanation of symbols: 10 is main memory, 11, 12, 13° 14 is processor, 15 is bus, 21 is data input register,
22 is a data bus check circuit. 23 is a bus driver, 24 is an enable signal generation circuit, 25 is an enable signal holding circuit, 26 is a microprogram control section, and 27 is an arithmetic section.

Claims (1)

[Claims] 1. In a distributed system in which a main memory and a plurality of microprogram-controlled processors are connected by a bus, each of the processors has a data input register connected to the bus, and an enable register that generates an enable signal under the control of the microprogram. a signal generation circuit; a bus driver having a function of sending internal data of the processor to the bus when the enable signal is input;
a data bus check circuit that checks the parity of the data when the data input register receives the contents of the bus or sends the data to the bus, and holds the result;
an enable signal holding circuit which receives the enable signal and the output signal of the data bus check circuit and holds the enable signal when a data parity error of the bus is detected; and the data bus check circuit which detects the error. If the enable signal is held,
A distributed processor system comprising means for storing the state of the enable signal holding circuit, which is error information, in an area on a main memory connected to the bus when the processor is on the sending side. .