JPS57125454A - System for processing of multiprocessor - Google Patents

System for processing of multiprocessor

Info

Publication number
JPS57125454A
JPS57125454A JP56010740A JP1074081A JPS57125454A JP S57125454 A JPS57125454 A JP S57125454A JP 56010740 A JP56010740 A JP 56010740A JP 1074081 A JP1074081 A JP 1074081A JP S57125454 A JPS57125454 A JP S57125454A
Authority
JP
Japan
Prior art keywords
test
processor
common storage
address
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56010740A
Other languages
Japanese (ja)
Other versions
JPS5853382B2 (en
Inventor
Hiroshi Oka
Kazuyuki Masuo
Yutaka Daidoji
Hiroshi Dewa
Takaharu Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP56010740A priority Critical patent/JPS5853382B2/en
Publication of JPS57125454A publication Critical patent/JPS57125454A/en
Publication of JPS5853382B2 publication Critical patent/JPS5853382B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)

Abstract

PURPOSE: To protect contents of a specific area of a common storage device, which is used by one processor by using a test and set flag for the request address of the common storage device and to make it possible that another processor writes data into this area when the processor is faulty.
CONSTITUTION: A test and set instruction is sent from plural processors 20W22 to a common storage controlling device 30 through a common bus 40 and is accepted by an order acceptance controlling circuit 60 of the device 30, and an address sent from common storage devices 10W12 is held in an address register 61. Data to be written in an address corresponding to contents of the register 61 is held in a data register 62, and a test and set flag from processors 20W22 is set to a test and set controlling circuit 63. Thus, contents of a specific area of devices 10W12 which is used by one of processors 20W22, and the fault of this processor is discriminated by the circuit 63 to permit another processor to write data into this area.
COPYRIGHT: (C)1982,JPO&Japio
JP56010740A 1981-01-29 1981-01-29 Multiprocessor processing method Expired JPS5853382B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56010740A JPS5853382B2 (en) 1981-01-29 1981-01-29 Multiprocessor processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56010740A JPS5853382B2 (en) 1981-01-29 1981-01-29 Multiprocessor processing method

Publications (2)

Publication Number Publication Date
JPS57125454A true JPS57125454A (en) 1982-08-04
JPS5853382B2 JPS5853382B2 (en) 1983-11-29

Family

ID=11758688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56010740A Expired JPS5853382B2 (en) 1981-01-29 1981-01-29 Multiprocessor processing method

Country Status (1)

Country Link
JP (1) JPS5853382B2 (en)

Also Published As

Publication number Publication date
JPS5853382B2 (en) 1983-11-29

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