JPH02101820A - Data conversion effectiveness deciding circuit - Google Patents

Abstract

PURPOSE:To output a data effective signal and to attain read of a correct data to a CPU by deciding whether a data is effective or ineffective depending on the detection of two retarded busy signals outputted from a flip-flop. CONSTITUTION:An input signal 1 before conversion is converted by a data converter 2 and goes to a converted digital data 3 and a busy signal 5 is outputted during data conversion. It is after a prescribed time after a busy signal 5 is ineffective that the conversion digital data 3 is stable and ensured. Thus, when a timing flip-flop 6 detects the busy signal 5, a 1st delay busy signal 19 is outputted in the timing of a reference timing 15 and a trigger signal 7 being a 2nd delay busy signal is outputted based thereupon, then the converted digital data 3 is fetched in a conversion data register 4 at a point of time of prescribed time delay after the detection of the busy signal 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a data conversion validity determination circuit that additionally outputs a determination signal as data to determine whether captured data is valid or invalid in a system that collects various digital data. It is related to.

[Conventional technology]

A block diagram of a conventional circuit of this kind is shown in FIG. 4. In the figure, 2 is an A/D (analog/digital) converter that converts the input signal l into digital data, and S/D C.
3 is converted digital data output from the data converter 2;
4 is a conversion data register that takes in the converted digital data 3, and 5 is B that is output by the data converter 2 during data conversion.
usy (converting) signal, 6 uses Busy signal 5,
A timing flip-flop outputs a trigger signal 7 at an appropriate timing to the conversion data register 4, and 8 is a bus.
It detects that the y signal 5 is output and outputs the data valid signal 9.
10 is a synchronization register that takes in the data valid signal 9 and the definite digital data 11 output from the conversion data register 4, 12 is a data output command from the central processing unit (CPU), and 13 is a reference timing 15. 14 is output digital data outputted from the synchronous register 10 by the synchronous output instruction 13, 16 is an output data valid signal outputted from the synchronous register 10 by the synchronous output instruction 13,
17 is a reset signal.

Next, the operation will be explained. An input signal 1 before conversion is converted by a data converter 2 to become converted digital data 3.

The data converter 2 outputs a Busy (converting) signal 5 while converting data. Converted digital data 3 after conversion
becomes stable and becomes definite data after a certain period of time after the Busy signal 5 becomes invalid, so after detecting the Busy signal 5 by the timing flip-flop 6 and further delaying it for a certain period of time by the reference timing 15, A trigger signal 7 is output, and the confirmed converted digital data 3 is taken into the converted data register 4.

At power-on, the contents of each register 4.10 are uncertain and the digital data 11.14 is invalid data. Therefore, an output instruction 12 from the CPU and a synchronous output instruction 13 synchronized with reference timing 15 indicate that the output digital data 14 output from the synchronous register 10 is invalid, so a reset instruction is output when the power is turned on. 17, the detection flip-flop 8 invalidates the data valid signal 9 and sends it to the synchronization register 10.

As described above, in this circuit, when the power is turned on, the data valid signal 9 is disabled, and the data converter 2 is turned on even once.
After outputting the 3usy signal 5, it is detected by the detection flip-flop 8 via the timing flip-flop 6 and the data valid signal 9 is output, so that the CPU can always read the converted digital data.

[Problem to be solved by the invention]

Since the conventional data conversion validity determination circuit is configured as described above, there is no change in the input signal 1 after the reset signal 17 outputted at power-on is released (
, if the data converter 2 does not output the Busy (converting) signal 5, the detection flip-flop 8 will not be able to detect the Busy signal 5 and will continue to output the data valid signal as an invalid signal, and the digital data 3.11.14 will be Despite the fact that the data is fixed, the CPU continues to issue the output command 12 over and over again, resulting in problems such as being unable to proceed to the next step and taking time.

This invention was made to solve the above-mentioned problems, and even if there is no change in the input signal, it is possible to read the correct data into the CPU as long as it is fixed data, and it can be configured with a small number of circuits. The purpose is to obtain a data conversion validity determination circuit.

[Means to solve the problem]

The data conversion validity determination circuit according to the present invention determines the output of the data validity signal to be output from the detection flip-flop by 13
This is done not only by detecting the usy signal, but also by detecting signals output from two timing flip-flops.

[Effect]

In this invention, after the reset signal 17 output at power-on is released, the B output from the data converter 2 is
Regardless of the presence or absence of the usy signal 5, after the determined converted digital data 3 is taken into the converted data register 4 based on the delayed signal of the busy signal 5, a valid signal is output as a data valid signal 9.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data conversion validity determining circuit according to an embodiment of the present invention, and in the figure, the same reference numerals as in the conventional circuit indicate the same or corresponding parts.

In the figure, 18 is the Q of the timing flip-flop 6.
This is an AND element that ANDs the C and Q terminal outputs. 19
is the first QC terminal output of timing flip-flop 6.
This is a delayed Busy signal.

Next, the operation of the circuit shown in FIG. 1 will be explained. An input signal 1 before conversion is converted by a data converter 2 to become converted digital data 3. Data converter 2 uses Bu during data conversion.
sy (converting) signal 5 is output. The converted digital data 3 after conversion becomes stable and final data is the Bus
Since it is a certain period of time after the y signal 5 becomes invalid,
When the timing flip-flop 6 detects the Busy signal 5, it outputs the first delayed Busy signal 19 at the reference timing 15, and further outputs the second delayed Busy signal 19 based on this.
By outputting the trigger signal 7, which is a delayed Busy signal, after the detection of the Busy signal 5, the determined converted digital data 3 is converted into converted data at a certain time delay, that is, at the rising edge of the trigger signal 7. Load into register 4.

Next, a description will be given with reference to the timing chart of FIG.

The detection flip-flop 8 invalidates and outputs the data valid signal 9 to the synchronization register 10 in response to the reset signal 17 at power-on. At this time, when the output instruction 12 from the CPU is detected by the timing flip-flop 6, the reference timing 15
Although the synchronous register 10 outputs the output digital data 14 and the output data valid signal 16 according to the synchronous output command 13 sampled at , it is found that the data is invalid.

When the data converter 2 is converting the input signal 1 and the Busy signal 5 is valid when the reset signal 17 is released (see Fig. 2(a)
l), the conversion data register 4 is activated by the first trigger signal 7.
latches the converted digital data 3, but at this time, the data valid signal 9 is invalid. Second trigger signal 7
is output a certain period of time after the Busy signal 5 becomes invalid, the conversion data register 4 launches the final data, and then the data valid signal 9 becomes valid.

When the reset signal 17 is released, the data converter 2 is outputting confirmed data, and when the Busy signal 5 is invalid (Fig. 2 (b)), the conversion data register 4 is confirmed by the first trigger signal 7. After the converted digital data 3 is latched, the data valid signal 9 becomes valid. Since the second trigger signal 7 is output a certain period of time after the Busy signal 5 becomes invalid, the conversion data register 4 latches the confirmed conversion digital data 3.

In the above embodiment, the data converter itself outputs B
Although the usy (converting) signal was used as a trigger signal to determine whether data is valid or invalid, it may also be used for a general data line with a separate circuit for detecting that data is being converted. It has the same effect as the example.

Another embodiment of the present invention having such a configuration is shown in FIG. In the figure, 20 is a data conversion detection circuit that detects that data conversion is in progress from converted digital data 3, and 21 is its output, a data conversion in progress signal, which is connected to AND element 8 and timing flip-flop 6. is entered.

〔Effect of the invention〕

As described above, according to the present invention, whether data is valid or invalid is determined not by detecting the Busy signal itself output from the data converter, but by detecting the two delayed E3usy signals output by the flip-flop. Since the configuration is configured to do this, if the digital data is fixed when the reset signal is released at power-on, the data valid signal is output after being latched in the register, so the CPU
This has the effect of being able to reliably convey that the data is correct.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data conversion validity determination circuit according to an embodiment of the present invention, FIG. 2 is a timing chart diagram showing the operation of the invention, and FIG. 3 is a data conversion validity determination circuit according to another embodiment of the invention. Block diagram showing the determination circuit, No. 4
The figure is a block diagram showing a conventional data conversion validity determination circuit. 1... Input signal, 2... Data converter, 3, 11° 14... Digital data, 4.10... Register, 5-Busy signal (first delayed Busy signal), 6...
・Timing flip-flop (timing detection means)
, 8...detection flip-flop (effective signal output means)
, 7... Trigger signal, 9, 16... Data valid signal, 12.13... Output command, 15... Reference timing, 17... Reset signal, 18... AND element,
19...first delayed Busy signal, 20 a data conversion detection circuit, and 21 a data conversion in progress signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A data conversion validity determination circuit in a system that collects various digital data includes a digital converter that converts an input signal to digital data, a conversion data register that takes in the converted data by the converter, and a converter that converts data. timing detection means for detecting a conversion-in-progress signal indicating that the conversion is in progress and outputting a trigger signal for loading data into the conversion data register, and determining whether the contents of the conversion data register are valid based on the output of the timing detection means Valid signal output means that determines whether the conversion signal is invalid and outputs a valid signal after a certain period of time has passed after the conversion signal becomes invalid; and a valid signal output means that synchronizes the confirmed data from the conversion data register with the valid signal. A data conversion validity determination circuit comprising: a synchronization register for outputting data.