JPS6267603A - Pulse measuring instrument - Google Patents

Abstract

PURPOSE:To eliminate the need for interruption processing by controlling the interruption of execution of a program with the status held and the restart of execution of an operation program of measured data in a CPU in accordance with a request signal due to termination of input pulse measurement. CONSTITUTION:In a pulse input device 600 provided on the same chip as the CPU of an executing part, input timings of plural pulses, for example, two pulses are measured by a pulse control circuit 640, a capture register 612, a free running counter 611, etc., to output a pulse trailing edge detection signal to an I/O request control part 900. Then, the request signal accompanied with termination of capture is supplied from the control part 900, and the CPU holds the status of the executing program and interrupts program execution in this state. A phase difference or the like of pulses is determined by operation in accordance with measured results from the device 600 and is stored, and the execution of the interrupted program is restarted thereafter. Thus, the interruption processing is unnecessary in the CPU side, and the use efficiency of the executing part is improved without complicating the constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device incorporating a pulse measuring device that measures the phase difference of input signals in order to control external equipment.

[Conventional technology]

In recent years, microcomputers have become highly integrated due to advances in LSI technology, and peripheral hardware such as DMA, timer/counter, serial interface, board, and A/D converter has come to be mounted on a single chip. Among them, devices equipped with pulse input/output devices are indispensable for controlling motors, etc., both in the consumer field such as VTRs, video discs, and CDs, and in the OA field such as printers, plotters, and floppy disks. be. In particular, the pulse measuring device measures various pulse signals output from external equipment, and is very important in controlling the number of revolutions, one rotation direction, and the like.

FIG. 4 is a block diagram of a conventional example of a microcomputer incorporating a pulse measuring device.

In this conventional example, the microcomputer 100 detects the falling edge of the pulse input to the pulse input signal line (hereinafter referred to as 1,000 channels) 1 and channel 2, and calculates the phase difference between the pulses input to channel 1 and channel 2. demand. At this time, in order to know the relative relationship between the pulses input to channel 1 and channel 2, if the falling edge of the input pulse of channel l is detected before the falling edge of the input pulse of channel 2. represents the phase difference as positive, and when the falling edge of the input pulse of channel 2 is detected before the falling edge of the input pulse of channel 1, the phase difference is represented as negative.

The microcomputer 100 has an execution section 101, a program memory 200, a data memory 300, an interrupt control section 400, and a pulse input device 500, all of which are connected to each other via an internal bus 700. Execution part 1
01 is a program counter (hereinafter referred to as PC) 10
2, a program status word (hereinafter referred to as PSW) 104 and a general-purpose register set 105.

The data memory 300 includes a PC 102 and a PSW 104.
, a status save area 391 for saving the contents of the general-purpose register set 105 (hereinafter referred to as status), a capture value storage area 351 for temporarily holding the previously captured value, an operation result storage area 361, and a software flag area 381 are set by software. has been done. In the software flag area 381, a software flag 382 and a software flag 383 are set corresponding to channel 1 and channel 2 in order to know the order of falling edge detection of the pulses input to channel 1 and channel 2. Flag 382.383 is
It is assumed that the value becomes "0" at the initialization stage during system startup. When the interrupt control unit 400 receives a falling edge detection signal via falling edge detection signal lines 531 and 532, which will be described later, it activates the respective interrupt control lines 401 and 402 to notify the execution unit 101 of an interrupt request.

The pulse input device is channel 1. A free-running power counter FRC5 that inputs a pulse signal from the outside via channel 2 and counts a predetermined count clock.
11, 52+, capture register 5.12.522 for temporarily holding counted data, and channel 1. It has a pulse control circuit 540 that detects the level of channel 2, detects the falling edge of the pulse signal input to channels 1 and 2, and outputs a falling edge detection signal to the interrupt control section 400.

This conventional example is for a case where the number of input channels is two, but if the number of external devices to be controlled becomes multiple and it becomes necessary to make the pulse input device multi-channel and perform multiple controls at the same time, this conventional example A pulse input device with the same configuration as the one can be used to create multiple channels.

Next, the operation of each hardware will be explained with reference to FIG.

When the pulse control circuit 540 of the pulse input device 500 detects the falling edge of channel l, the value of the FRC 511 is transferred to the capture register 5 in synchronization with this detection timing.
12, and the interrupt control unit 400 outputs a falling edge detection signal to indicate that one capture operation is completed.
to notify. Similarly, when the pulse control circuit 540 detects the falling edge of channel 2, the value of the FRC521 is transferred to the capture register 5 in synchronization with this detection timing.
22 and outputs a falling edge detection signal 532. The interrupt control unit 400 receives the falling edge detection signal 5.
31 is input, the interrupt control line 401 is activated, and when a falling edge detection signal 532 is input, the interrupt control line 402 is activated and requests an interrupt to the execution unit 101. The execution unit 101 normally reads and executes instructions on the program memory 200 addressed by the PC 102, and stores processing data on the data memory 300.
Interrupt control lines 401.40 are activated each time execution of one instruction is completed.
2 is sampled, and if it is inactive, the above operation is repeated, and if the interrupt control lines 401 and 402 are active, a capture end interrupt process is executed to transfer or process the captured data.

Next, software processing will be explained with reference to the flowchart in FIG.

First, a case where the interrupt control line 401 becomes active will be described.

When the execution of one instruction is completed, the execution unit 101 samples the interrupt control lines 401 and 402, and
If 402 is active, the process moves to interrupt processing and saves status information to the status save area 391 in order to maintain the state of the program currently being executed (processing 1).

Subsequently, an interrupt processing program is started. The interrupt service program first reads the software flags 382 and 383 from the software flag save area 381. ), then checks whether the interrupt control line 401 is active (process 3), and if the interrupt control line 401 is active, checks the software flag 383 corresponding to channel 2 (process 4). If the software flag 383 is 0'', the pulse control circuit 5
Since the falling edge of channel 2 is not detected before the falling edge of channel 1 is detected, 40 stores the value of the capture register 512 in the capture value storage area 3.
51 (processing 6) and setting the software flag 382 indicating that the pulse control circuit 540 has detected the falling edge of channel l to "°1" (processing 7). After that, the status information is transferred to the status save area 391. (processing 8), ends the capture end interrupt service program, and returns to execution of the main program. if,
If the software flag 383 is "1", the pulse control circuit 540 has already detected the falling edge signal of channel 2. Therefore, the capture register 52 held at the falling edge detection timing of channel 2
Since the value of 2 is stored in the capture value storage area 351, process 9 subtracts (the value of the capture register 512) from (the value of the capture value storage area 351) and stores the calculation result in the calculation result storage area 381. ), the software flag 383 is set to "O" (process 10). Thereafter, the status is restored (process 11), and a capture completion interrupt request is generated to perform processing based on the calculation result obtained by the capture completion interrupt (process 12). Next, a case where the interrupt control line 402 becomes active will be described. In this case, the above-mentioned interrupt control line 401
The interrupt processing program is activated in the same way as when the interrupt processing program becomes active.

The interrupt service program first reads the software flags 381, 382, and 383 (process 2), checks whether the interrupt control line 402 is active corresponding to channel l in the interrupt service program (process 3), and reads the interrupt control line 3). If 402 is active, the software flag 382 is checked (processing 5).

If the software flag 382 is "O", the pulse control circuit 540 has not detected the falling edge of the channel E signal before detecting the falling edge of channel 2, so the value of the capture register 522 is stored as a capture value. The data is transferred to the area 351 (processing 13). Also, the software flag 383, which indicates that the pulse control circuit 540 has detected the falling edge of channel 2, is set to 1" (processing 14), and the status is restored (processing 15). Return to running the program. Software flag 382 is 1'''
If so, the value of the capture register 512 held at the falling edge detection timing of channel 1 is stored in the capture value storage area 351, so from (the value of the capture register 522)
1 value) and store the calculation result in the calculation result storage area 361.
(Process 16) 0 Next, software flag 3
After setting 82 to 0'' (process 17) and returning the status (process 11), a capture completion interrupt request is generated (
Processing 12).

Through the above processing, it is possible to measure the phase difference between the signal input to channel I and the signal input to channel 2, and also to determine the phase difference between the signal input to channel I and the signal input to channel 2, depending on the sign of the phase difference.
It is possible to identify which of the input signals is leading.

[Problem that the invention seeks to solve]

The conventional pulse meter IJA device described above executes the process of transferring or calculating captured values by software processing using interrupts, so the PC, psw, and general-purpose registers are saved every time a capture is performed, and the interrupt During processing, interrupt processing is performed by conditional branching based on software flags, and after the interrupt processing is completed, the PC is restarted.
, PSW, it is necessary to restore the general-purpose registers,
When the number of objects to be controlled increases, processing such as saving and restoring the PC, PSW, and general-purpose registers increases, and the execution unit spends more time on processing that is not originally intended.
It has the disadvantage of reducing the processing power of the execution part, and
When increasing the number of channels to accommodate a large number of control targets, it is necessary to provide the same number of free-running counters and capture registers as there are channels, which increases the amount of hardware due to the complexity of wiring, etc. There are drawbacks.

[Means for solving problems]

The pulse measuring device of the present invention is a semiconductor information processing device in which at least a central processing unit, a data memory for storing data, and a pulse input device are integrated on a single semiconductor substrate. In addition to measuring the input timing, a measurement end processing request is output to the central processing unit each time the measurement of the input timing of the plurality of pulses is completed, and the central processing unit executes the program according to the pulse measurement end processing request. After interrupting the execution of the program while retaining the status information indicating the execution state, and performing calculation and processing of the measurement data and data storage processing in the data memory based on the information of the pulse input device, The feature is that the execution process of the interrupted program is resumed.

In this way, by transferring or calculating captured values without using an interrupt, the PC, PSW, and general-purpose registers can be saved and saved every time the capture performs a capture operation.
Since it does not perform processing such as return, it reduces the time spent on processing that is not originally intended, such as saving and restoring PC, psw, and general-purpose registers, which can be problematic when the number of input channels increases, and improves the efficiency of execution unit usage. In addition, when the number of input channels increases, it is possible to easily support a large number of input channels by simply setting a macro service channel, and there is no need to add FRC or capture registers, reducing the amount of hardware used. You can save money.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a microcomputer incorporating a pulse measuring device according to the present invention, FIG. 2 is a block diagram of a pulse input device 600 in FIG. 1, and FIG. 3 is a block diagram of a pulse input device 600 in FIG. 9 is a timing chart of the I10 request control unit 900 of FIG.

The microcomputer 100 has an execution unit 101. It has an I10 request control section 900 and a pulse input device 1800.

These are connected to each other via an internal bus 700. The execution unit 101 includes a program memory 200 that stores programs, and a data memory 300 that stores processing data.
, a PC 102 indicating the address of the program to be executed next, an arithmetic and logic unit (hereinafter referred to as A) having an arithmetic and logic operation function;
(denoted as LU) 103, PSW 104. which indicates the operating state of the entire execution unit. A general-purpose register 105 that holds data being processed, an instruction register 1o6 that holds instructions to be executed, and an execution control unit 108 that controls the entire execution unit according to the contents of the instruction register 106. I10 Accept request I
10 request reception units 150. The data memory 300 has a transfer area pointer 301 and a data transfer area 302.

In this embodiment, the address of the data transfer area 302 is stored in advance in the transfer area pointer 301 by software. When the I10 request control unit 900 receives a falling edge detection signal, which will be described later, the capture end I10 request signal line 810 to notify the execution unit 101 of a pulse measurement end process request.

As shown in FIG. 2, the pulse input device 600 receives pulse signals of two channels, channel 1 and channel 2. register 6!2, pulse control circuit 640, edge detection signal line 631 for detecting a falling edge of channel 1 or channel 2 and outputting an edge detection signal to I10 request control section 900, and execution section 101. A channel signal line 63 for outputting channel signals and terminal level signals to
2 and a terminal level signal line 633.

Next, the operations of the pulse input device 800 and the I10 request control section 900 will be explained with reference to the timing chart of FIG. FIG. 3(a) is a timing chart when the phase of the pulse signal input to channel 1 is ahead of the phase of the pulse signal input to channel 2, and FIG. 3(b)
is a case where the phase of the input pulse signal of channel 2 leads the phase of the input pulse signal of channel 1.

Pulse control circuit 640 is configured to control channel 1 or channel 2.
Falling edge detection timing tl.

t2. The value of FRC811 is transferred to the capture register 612 in synchronization with ta and ta, and the edge detection signal line 8
Activate 31. In addition, the pulse control circuit 640
When the falling edge of channel 1 is detected at the timing of tl or ta, the channel signal line 632 and the terminal level signal line 83 are synchronized with the timing of tl and ta.
3 respectively, outputs "1" and the terminal level of channel 2, and similarly outputs "1" and the terminal level of channel 2 at t2. When the falling edge of channel 2 is detected at timing ta, “O” is applied to channel signal line 832 and terminal level signal line 633 at timing t2°ta.
'' and the terminal level of channel l. When the pulse control circuit 640 activates the edge detection signal line 631 at the timing tl, the I10 request control unit 900 outputs
Connect the capture end I10 request signal line 910 to tl<t
Activate at timing a and pulse input device 6
00 notifies the execution unit 101 that the capture operation has ended. The I10 request control unit 900 performs t2. ta,
Similarly, the capture end I10 request signal line 810 is activated at the timings tb, tc, and td leading to ta. The I10 request control unit 900 also accepts I10 requests from other peripheral hardware, but this is omitted in this embodiment.

Next, the operation of the execution unit 101 will be explained.

When the I10 request receiving unit 150 detects that the capture termination request signal line 310 has become active,
The execution unit 101 executes the capture end I10 request process.In this embodiment, the capture end I10 request is not processed by an interrupt, but the execution unit 101 interrupts program execution and transfers or performs arithmetic operation while retaining status information. It is processed by doing the following. Below, this I1
The processing form for 0 requests is referred to as a macro service.

The macro service processing of this embodiment has two processing forms described below.

■Data transfer area 302 pointed to by transfer area pointer 301
The value of the capture register 812 is transferred to.

(2) Subtract the contents of the data transfer area 302 pointed to by the transfer area pointer 301 from the value of the capture register θ12, set the value of the channel signal line 632 as the sign of the subtraction result, and then transfer to the data transfer area 302.

Next, referring to the timing charts of FIGS. 1, 2, and 3, the execution unit 10 when performing macro service processing will be described.
The operation of step 1 will be explained.

The execution unit 101 normally executes P on the program memory 200.
The instruction code is read from the address pointed to by C102, transferred to the instruction register 10Ei, and the execution control unit 10B outputs various control signals to execute l instructions, and each time one instruction is executed, the next instruction to be executed is changed. pC102 is updated to the address of . The I10 request reception unit 150 samples the capture end I10 request signal line 910 every time one instruction is completed,
When inactive, repeat the above operation.

Next, the operation of the execution unit 101 when the capture end I10 request signal line 910 becomes active at timing ta will be described. When the I10 request reception unit 150 detects that the capture end I10 request signal line 810 has become active at the timing ta, it samples the channel signal line 832 and the terminal level signal line 633 at the timing ta, and outputs the terminal level signal line. Since 633 is at a high level at the timing of ta, the capture ends I10.
It recognizes that the request is a transfer processing request, and forcibly transfers the processing code of the macro service that transfers the value of the capture register 812 to the instruction register 106.

The execution control unit 108 prohibits updating of the address of the PC 102, and updates the PC 102, P5W104, and general-purpose register 1.
The following process is started while maintaining the state of 05.

(2) The execution control unit 108 reads the value of the transfer area pointer 301 and selects the data transfer area 302 pointed to by the transfer area pointer 301.

(2) The execution control unit 108 transfers the value of the FRC 611 at the timing of tl held by the capture register 812 to the data transfer area 302.

■p Release the address update prohibition of C102 and return to the original program execution operation.

Next, the operation of the execution unit 101 when the capture end I10 request signal line 910 becomes active at timing tb will be described. The operation from when the I10 request receiving unit 150 detects the capture end I10 request signal to sampling the channel signal line 632 and the terminal level signal line 633 is as follows.
Capture ends at timing ta I10 request signal line 8
10 becomes active. The I10 request accepting unit 150 recognizes that the capture end I10 request is an arithmetic processing request because the terminal level signal line 633 is at a low level at timing tb, and sends the macro service processing code for performing the arithmetic operation to the instruction register 101.
Force setting to 3. The execution control unit 10B is a PC1
02 address update is prohibited and PC102, PSW1
04. The following processing is performed while maintaining the state of the general-purpose register 105.

(2) The execution control unit 108 reads the value of the transfer area pointer 301 and selects the data transfer area 302 pointed to by the transfer area pointer 301.

■The execution control unit 108 uses the ALU 103 to transfer data from the data transfer area 302 from the value of the capture register 612.
Subtract the value of. That is, the value of FRC811 at the timing of t2 and the value of FRC at the timing of tl
Find the difference between the 811 values.

■The execution control unit 108 uses the ALU 103 to convert the sign of the subtraction result to the value of the channel signal @832, that is, “
Set it to 0”.

(2) The execution control unit 108 transfers the signed subtraction result to the data transfer area 302.

Through the above processing, F RC at timing t2
FRCEill at the value of 811 and the timing of tl
The difference between the values of , that is, TI, can be determined, and from the sign of T1, it can be known that the signal of channel 1 is ahead of the signal of channel 2, and from the value of T1, it can be known that the phase difference. Therefore, the execution unit 101 activates a capture completion interrupt to perform processing based on the calculation data.

Capture ends at timing tc I10 request signal line 9
The operation of the execution unit 101 when 10 becomes active is as follows.
This is similar to the operation of the execution unit 101 when the capture end I10 request signal line 910 becomes active at the timing ta described above. Furthermore, when the capture end I10 request signal line 910 becomes active at the timing td, the operation of the execution unit 101 is to end the capture at the timing tb, except that the value of the channel signal line 632 is "1". The operation is similar to the operation of the execution unit 101 when the request signal line 810 becomes active. From the sign of T2 determined by the above operation, we can know that the channel 2 signal is ahead of the channel 1 signal, and from the T2 value we can know the phase difference between the channel l signal and the channel 2 signal. .

In this embodiment, if the number of channels increases, this can be easily handled by simply setting a data transfer area and a transfer area pointer for each channel.

〔Effect of the invention〕

As explained above, the present invention transfers or calculates captured values without using an interrupt, so that processes such as saving and restoring the PC, psw, and general-purpose registers are not performed every time the capture performs a capture operation. , it is possible to reduce the time spent on processing that is not originally intended, such as saving and restoring PC, psw, and general-purpose registers, which are problematic when the number of input channels increases, and improve the efficiency of use of the execution section. When the number of input channels increases, it is possible to easily handle a large number of input channels by simply setting macro service channels, and there is no need to add FRC or capture registers, which has the effect of saving the amount of hardware used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the pulse measuring device of the present invention, and FIG. 2 shows the pulse input device 600 in FIG. 1.
and a more detailed block diagram of the I10 request control unit 300,
FIG. 3 is a timing chart showing the operation of the pulse measuring device in this embodiment, FIG. 4 is a block diagram of the conventional pulse measuring device, and FIG. 5 is a flowchart of interrupt processing in the conventional example. 1... Channel, 2... Channel, 100... Microcomputer, 101... Execution unit, 102... Program counter (PC), 103...
- Arithmetic and logic operation unit) (ALU), 104... Program status save area (PSW), 105... General purpose register, 106... Instruction register. 108... Execution control unit, 150... I10 request reception unit, 200... Program memory, 300... Data memory, 301... Transfer area pointer, 302... Data transfer area, 351... - Capture value storage area, 381... Calculation result storage area, 381... Software flag area, 382... Software flag (for channel 1), 383... Software flag (for channel 2), 391...・Status save area, 400... Interrupt control unit, 401, 402... Interrupt control line, 500... Pulse input device, 511, 521... Free running counter (FR
C), 512, 522...Capture register・531, 5
32... Hidogarie 7 detection signal line 540... Pulse control circuit. eoo...Pulse input table. 611...Free running counter (FRC), 61
2...Capture register. 631... Falling edge detection signal line 632...
Channel signal lines 633...Terminal level signal line, 640...Pulse control circuit, 700...Internal bus, 900...I10 request control section, 910...Capture end I10 request signal line. Figure 5

Claims (1)

[Claims] In a semiconductor information processing device in which at least a central processing unit, a data memory for storing data, and a pulse input device are integrated on a single semiconductor substrate, the pulse input device measures the input timing of a plurality of pulse signals, and A measurement end processing request is output to the central processing unit each time measurement of the input timing of the plurality of pulses is completed, and the central processing unit retains status information indicating the execution state of the program according to the pulse measurement end processing request. The execution of the program is interrupted while the program is being held, and after performing arithmetic processing of the measurement data and data storage processing in the data memory based on the information of the pulse input device, the execution processing of the interrupted program is resumed. A pulse measuring device characterized by: