JPH0812561B2 - Pulse interval measuring device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus having a pulse interval measuring device for measuring a phase difference between input signals for controlling an external device.

[Conventional technology]

In recent years, microcomputers have been highly integrated due to the progress of LSI technology, and peripheral hardware such as DMA, timer / counter, serial interface, port, and A / D converter have been mounted on one chip. Among them, those equipped with pulse input / output devices are indispensable for controlling motors in both consumer fields such as VTRs, video disks, and CDs, and OA fields such as printers, plotters, and floppy disks. is there.
In particular, the pulse interval measuring device measures various pulse signals output from an external device, and is very important in performing control such as rotation speed control and rotation direction control.

FIG. 4 is a block diagram of a conventional example of a microcomputer incorporating a pulse interval measuring device.

In this conventional example, the microcomputer 100 detects the falling edges of the pulses input to the pulse input signal line (hereinafter referred to as channel) 1 and channel 2, and obtains the phase difference between the pulses input to channel 1 and channel 2. . At this time, if the falling edge of the input pulse of channel 1 is detected before the falling edge of the input pulse of channel 2 so that the relative relationship between the pulses input to channel 1 and channel 2 can be known. Performs a process of expressing the phase difference as a positive value and expressing the phase difference as a negative value when the falling edge of the input pulse of channel 2 is detected before the falling edge of the input pulse of channel 1.

The microcomputer 100 has an execution unit 101, a program memory 200, a data memory 200, an interrupt control unit 400, and a pulse input device 500, all of which are connected to each other via an internal bus 700. The execution unit 101 includes a program counter (hereinafter referred to as PC) 102, a program status word (hereinafter referred to as PSW) 104, and a general-purpose register set.
Has 105. The data memory 300 includes PC102, PSW104,
A status save area 391 for saving the contents of the general-purpose register set 105 (hereinafter, referred to as status), a capture value storage area 351 for temporarily holding a previously captured value,
The calculation result storage area 361 and the software flag area 381 are set by software. In the software flag area 381, the software flag 382 and the software flag 383 are set in correspondence with the channel 1 and the channel 2 in order to know the order of the fall detection of the pulses input to the channel 1 and the channel 2. These software flags 382 and 383 are set to "0" at the initialization stage at system startup. When the interrupt control unit 400 receives the falling edge detection signals via the falling edge detection signal lines 531 and 532, which will be described later, the interrupt control line 40 respectively.
1, 402 is activated and the execution unit 101 is notified of the interrupt request.

The pulse input device inputs a pulse signal from outside via channel 1 and channel 2, and is a free running counter FRC511, 5 that counts a predetermined count clock.
21, the capture registers 512 and 522 for temporarily holding the counted data, the level detection of channel 1 and channel 2 and the falling edge of the pulse signal input to channel 1 and channel 2 to detect the falling edge in the interrupt control unit 400. It has a pulse control circuit 540 for outputting a signal.

This conventional example is a case where the number of input channels is two, but when there are a plurality of control targets of the external device and it is necessary to make the pulse input device multi-channel and perform a plurality of controls at the same time, this conventional example The pulse input device has the same configuration as the above, but has multiple channels.

Next, the operation of each hardware will be described with reference to FIG.

The pulse control circuit 540 of the pulse input device 500 is channel 1
When the falling edge of is detected, the value of FRC511 is stored in the capture register 512 in synchronization with this detection timing, the falling edge detection signal is output, and the interrupt control unit 400 is notified that one capture operation is completed. Notice.
Similarly, when the pulse control circuit 540 detects the falling edge of channel 2, the FRC5 is synchronized with this detection timing.
The value of 21 is stored in the capture register 522, and the falling edge detection signal 532 is output. When the falling edge detection signal 531 is input, the interrupt control unit 400 activates the interrupt control line 401, and when the falling edge detection signal 532 is input, the interrupt control line 402 is activated to request the execution unit 101 for an interrupt. The execution unit 101 normally reads and executes an instruction in the program memory 200 addressed by the PC 102 and stores the processed data in the data memory 300, but samples the interrupt control lines 401 and 402 each time the execution of one instruction is completed. , If it is inactive, repeat the above operation,
If the interrupt control lines 401 and 402 are active, a capture end interrupt process for transferring or processing the captured data is executed.

Next, the software processing will be described with reference to the flowchart of FIG.

First, a case where the interrupt control line 401 becomes active will be described.

The execution unit 101 samples the interrupt control lines 401 and 402 when the execution of one instruction is completed. If the interrupt control lines 401 and 402 are active, the execution unit 101 shifts to interrupt processing and holds the status information to hold the state of the program currently being executed. It is saved in the save area 391 (process 1). Then, the interrupt processing program is started. The interrupt service program first reads the software flags 382 and 383 from the software flag save area 381 (process 2), then checks whether the interrupt control line 401 is active (process 3), and checks whether the interrupt control line 401 is active. For example, the software flag 383 corresponding to channel 2 is checked (process 4). If the software flag 383 is “0”, the pulse control circuit 540 has not detected the falling edge of the channel 2 before detecting the falling edge of the channel 1. The captured data is transferred to the capture value storage area 351 (process 6) and the software flag 382 indicating that the pulse control circuit 540 has detected the falling edge of channel 1 is set to "1" (process 7). After that, the status information is displayed in the status save area 39
The process returns from 1 (process 8), ends the capture end interrupt service program, and returns to the execution of the main program. If the software flag 383 is "1", the pulse control circuit 540 has already detected the falling edge signal of channel 2. Therefore, the capture register held at the falling edge detection timing of channel 2
Since the value of 522 is stored in the capture value storage area 351, the value of the capture register 512 is subtracted from the value of the capture value storage area 351, and the calculation result is stored in the calculation result storage area 361. 9), software flag 383
Is set to "0" (Processing 10). After this, the status is restored (process 11), and a capture completion interrupt request for performing processing based on the operation result obtained by the capture end interrupt is generated (process 12). Then, the interrupt control line 402
Will be described when is activated. In this case, the interrupt processing program is activated in the same manner as when the interrupt control line 401 described above becomes active. The interrupt service program starts with software flag 38.
Read software flags 382 and 383 from 1 (Process 2),
The interrupt service program checks whether the interrupt control line 402 corresponding to channel 1 is active (process 3). If the interrupt control line 402 is active, the software flag 382 is checked (process 5).

If the software flag 382 is “0”, the pulse control circuit 540 has not detected the falling edge of the channel 1 signal before detecting the falling edge of the channel 2, and therefore the value of the capture register 522 is changed. Transfer to the capture value storage area 351 (process 13). Further, the pulse control circuit 540 sets the software flag 383 indicating that the falling edge of the channel 2 has been detected to "1" (process 14), restores the status (process 15), and returns to program execution. If the software flag 382 is "1", the value of the capture register 512 held at the falling edge detection timing of channel 1 is stored in the capture value storage area 351, and therefore (the value of the capture register 522) is changed to ( The value of the capture value storage area 351) is subtracted, and the calculation result is stored in the calculation result storage area 361 (process 16). next,
After the software flag 382 is set to "0" (process 17) and the status is returned (process 11), a capture completion interrupt request is generated (process 12).

With the above processing, the phase difference between the signal input to channel 1 and the signal input to channel 2 can be measured, and which of the signal input to channel 1 and the signal input to channel 2 is advanced depending on the sign of the phase difference. Can be identified.

[Problems to be solved by the invention]

The above-described conventional pulse interval measuring device performs the process of transferring or calculating the captured value by the software process by the interrupt, so that the PC, PSW, and the general-purpose register are saved each time the capture is performed, and During interrupt processing, interrupt processing is performed by conditional branching with a software flag, and after interrupt processing is completed, PC, PS again
W, processing to restore general-purpose registers becomes necessary, and when the number of controlled objects increases, the processing such as saving and restoring PC, PSW, general-purpose registers will increase, and the execution unit will not perform these original processing. This has the disadvantage that it consumes a lot of time and reduces the processing capacity of the execution unit.In addition, if channels are added to support many control targets, it is necessary to provide free running counters and capture registers as many as the number of channels. However, there is a drawback that the amount of hardware becomes enormous due to complicated wiring.

[Means for solving problems]

A pulse interval measuring device of the present invention is a program memory,
An execution unit including a data memory, an I / O request reception unit, an instruction execution unit, a program counter, and a program status word indicating an execution operation state, a counter that counts clocks, a capture register, and first and second pulses When a signal is received, a detection signal is generated each time a predetermined inversion edge appears in these pulse signals, and the contents of the counter at that time are stored in a capture register, and a pulse signal in which a predetermined inversion edge appears Is a pulse input device having a pulse control circuit that generates a level signal having a logic level based on the level at the time when the inversion edge of a different pulse signal appears, and I / O request acceptance of the execution unit in response to the detection signal The I / O request control unit that issues processing requests to the I / O request receiving unit When the level signal is the first logic level, the macro service processing code designating the first form is supplied to the instruction executing means, and when the level signal is the second logic level, the macro service processing code designating the second form is supplied to the instruction executing means. The instruction executing means, in response to the macro service processing code, prohibits the address update of the program counter and interrupts the execution of the program, and the information of the program counter and the program status word at that time is not saved in the data memory as it is. In this state, when the macro service processing code indicates the first form, the contents of the capture register are transferred to the data transfer area in the data memory, and when the macro service processing code indicates the second form, the contents of the data transfer area and the capture register are transferred. The operation of the contents and is executed and the contents of the operation result are stored in the data memory. Transferred to over data transfer area, then, characterized in that it resumes execution of the program was interrupted.

In this way, the number of input channels is increased because the captured value is transferred or calculated independently of interrupts, and the PC, PSW, general-purpose register save and restore processing is not performed each time the capture performs a capture operation. If you do, you can reduce the time spent for processing that is not originally intended, such as saving and restoring of PC, PSW, general-purpose registers, etc., improving the usage efficiency of the execution unit, and if the number of input channels increases, You can easily support a large number of input channels simply by setting the macro service channel, and you do not need to add an FRC or capture register, so you can save the amount of hardware used.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a microcomputer incorporating the pulse interval measuring device of the present invention, and FIG.
FIG. 3 is a block diagram of the pulse input device 600 in FIG.
The figure is a timing chart of the I / O request control unit 900 of the pulse input device 600.

The microcomputer 100 has an execution unit 101, an I / O request control unit 900, and a pulse input device 600, which are internal buses 70.
Connected to each other through 0. The execution unit 101 includes a program memory 200 that stores a program, a data memory 300 that holds processing data, a PC 102 that indicates an address of a program to be executed next, an arithmetic logic operation unit (hereinafter referred to as ALU) having an arithmetic logic operation function. 103, PSW 104 indicating the operation state of the entire execution unit, general-purpose register 105 for holding data being processed, instruction register 1 for holding an instruction to be executed
06, an execution control unit 108 that controls the entire execution unit according to the contents of the instruction register 106, an I / O request reception unit 1 that receives an I / O request
Having 50. The data memory 300 has a transfer area pointer 301.
And a data transfer area 302. In this embodiment, the address of the data transfer area 302 is stored in advance in the transfer area pointer 301 by software. I / O request controller 90
When 0 receives a falling edge detection signal described later, it activates the capture end I / O request signal line 910 and notifies the execution unit 101 of the pulse measurement end processing request.

As shown in FIG. 2, the pulse input device 600 inputs the pulse signals of channel 1, channel 2 and 2 channels, the signal lines of channel 1 and channel 2, the free running counter (FRC) 611, and the capture. Register 612
An edge detection signal line 631 for detecting a falling edge of channel 1 or channel 2 and outputting an edge detection signal to the I / O request control unit 900.
And a channel signal line 632 and a terminal level signal line 633 for outputting a channel signal and a terminal level signal to the execution unit 101.

Next, the operations of the pulse input device 600 and the I / O request control unit 900 will be described with reference to the timing chart of FIG. 3 (a) is a timing chart when the phase of the pulse signal input to channel 1 leads the phase of the pulse signal input to channel 2, and FIG. 3 (b) is the input pulse of channel 2 This is the case where the phase of the signal leads the phase of the input pulse signal of channel 1.

The pulse control circuit 640 can be used for channel 1 or channel 2.
The value of the FRC 611 is transferred to the capture register 612 in synchronization with the falling edge detection timings t1, t2, t3, and t4, and the edge detection signal line 631 is activated. When the pulse control circuit 640 detects the falling edge of channel 1 at the timing of t1 or t4, the pulse control circuit 640 outputs “1” to the channel signal line 632 and the terminal level signal line 633 in synchronization with the timing of t1 and t4. Similarly, when the terminal level of channel 2 is output and the falling edge of channel 2 is detected at the timing of t2 and t3, the channel signal line 632 is detected at the timing of t2 and t3.
And "0" and the terminal level of channel 1 are output to the terminal level signal line 633. The pulse control circuit 640 uses the edge detection signal line 6
When 31 is activated at the timing of t1, the I / O request control unit 900 activates the capture end I / O request signal line 910 at the timing of ta following t1, and the pulse input device
The execution unit 101 is notified that the 600 has completed the capture operation. The I / O request control unit 900 also activates the capture end I / O request signal line 910 at the timings tb, tc, and td following t2, t3, and t4. The I / O request control unit 900 accepts I / O request signals from other peripheral hardware as well,
It is omitted in this embodiment.

 Next, the operation of the execution unit 101 will be described.

The I / O request receiving unit 150 displays the capture end I / O request signal line 9
When detecting that 10 is activated, the execution unit 101
Executes the capture end I / O request process. In the present embodiment, the capture end I / O request is not processed by an interrupt, but is executed by the execution unit 101 interrupting the execution of the program and performing a transfer or arithmetic operation while holding the status information. Hereinafter, the processing form of this I / O request will be referred to as a macro service.

The macro service processing of this embodiment has the following two processing modes.

The value of the capture register 612 is transferred to the data transfer area 302 indicated by the transfer area pointer 301.

Transfer area pointer 301 from the value of capture register 612
The content of the data transfer area 302 indicated by is subtracted, the value of the channel signal line 632 is set to the sign of the subtraction result, and then the data is transferred to the data transfer area 302.

Next, referring to the timing charts of FIG. 1, FIG. 2 and FIG. 3, the execution unit 101 at the time of performing macro service processing
Will be described.

The execution unit 101 normally reads an instruction code from the address pointed to by the PC 102 on the program memory 200, transfers it to the instruction register 106, and the execution control unit 108 outputs various control signals to execute one instruction. Every time an instruction is executed, the PC 102 is updated with the address of the next instruction to be executed. I / O request reception part 15
0 indicates the capture end I / O request signal line 91 at the completion of one instruction
Samples 0, and repeats the above operation when inactive.

Next, the operation of the execution unit 101 when the capture end I / O request signal line 910 becomes active at the timing of ta will be described. When the I / O request reception unit 150 detects that the capture end I / O request signal line 910 has become active at the timing of ta, it samples the channel signal line 632 and the terminal level signal line 633 at the timing of ta, and Level signal line 633 is ta
The high level at the timing of recognizing that the capture end I / O request is a transfer processing request, and the processing code of the macro service for transferring the value of the capture register 612 is forcibly transferred to the instruction register 106. To do. That is, as described above, since the I / O request receiving unit 150 samples the capture end I / O request signal line 910 every time one instruction is completed, the receiving unit 150 sends the next instruction to the instruction register 106. Before being stored, the processing code of the macro service provided therein is forcibly transferred to the instruction register 106. Since the macro service processing code is stored in the instruction register 106 in this way, the completion control unit prohibits the address update of the PC 102 and starts the following processing while maintaining the states of the PC 102, PSW 104, and general-purpose register 105. To do.

The execution control unit 108 reads the value of the transfer area pointer 301 and selects the data transfer area 302 pointed to by the transfer area pointer 301.

The execution control unit 108 transfers the value of the FRC 611 held by the capture register 612 at the timing of t1 to the data transfer area 302.

The address update prohibition of the PC 102 is released, and the original program execution operation is resumed.

Next, capture end I / O request signal line 9 at tb timing
The operation of the execution unit 101 when 10 becomes active will be described. The operation until the I / O request receiving unit 150 detects the capture end I / O request signal and samples the channel signal line 632 and the terminal level signal line 633 is the capture end I / O request signal line at the timing of ta. This is the same as when the 910 becomes active. The I / O request receiving unit 150 uses the terminal level signal line 633.
Recognizes that the capture end I / O request is an arithmetic processing request, since is at the low level at the timing of tb,
The macro service processing code for performing the operation provided therein is forcibly set in the instruction register 106. The execution control unit 108 prohibits the address update of the PC 102 and
2. The following processing is performed while holding the states of PSW 104 and general-purpose register 105.

The execution control unit 108 reads the value of the transfer area pointer 301 and selects the data transfer area 302 pointed to by the transfer area pointer 301.

The execution control unit 108 uses the ALU 103 to subtract the value of the data transfer area 302 from the value of the capture register 612. That is, the difference between the value of FRC611 at the timing of t2 and the value of FRC611 at the timing of t1 is obtained. ALU1 at this time
The calculation state of 03 is not taken into PSW104 because changing the contents of PSW104 is prohibited.

The execution control unit 108 uses the ALU 103 to set the sign of the subtraction result to the value of the channel signal line 632, that is, “0”.

The execution control unit 108 transfers the signed subtraction result to the data transfer area 302.

By the above processing, the difference between the value of FRC611 at the timing of t2 and the value of FRC611 at the timing of t1, that is,
T1 can be obtained, and the sign of T1 indicates that the signal of channel 1 is ahead of the signal of channel 2, and
The phase difference can be known from the value of T1. Then the execution unit 10
1 activates the capture completion interrupt for processing based on the operation data. In this capture completion interrupt, the contents of the PC 102, PSW 104, and general-purpose register 105 are saved in the stack area of the data memory 300, and the vector address for starting the capture completion interrupt processing program is specified in the PC 102. Thus, the execution unit 101 executes the capture completion interrupt processing program stored in the program memory 200 and performs a predetermined process. After the processing, the saved contents of the PC 102, PSW 104, and general-purpose register 105 are restored, and the original program that was interrupted is restored.

When the capture end I / O request signal line 910 becomes active at the timing of tc, the operation of the execution unit 101 is as described above.
The operation is the same as that of the execution unit 101 when the capture end I / O request signal line 910 becomes active at the timing a.
At the timing of td, the capture end I / O request signal line 9
The operation of the execution unit 101 when 10 becomes active is when the capture end I / O request signal line 910 becomes active at the timing of tb, except that the value of the channel signal line 632 is "1". The operation is the same as that of the execution unit 101. From the code of T2 obtained by the above operation, the signal of channel 2 is ahead of the signal of channel 1, and T2
The phase difference between the channel 1 signal and the channel 2 signal can be known from the value of.

In the present embodiment, when the number of channels is increased, it is possible to easily cope with it by setting the data transfer area and the transfer area pointer for each channel.

〔The invention's effect〕

As described above, according to the present invention, the captured value is transferred or calculated without depending on the interrupt, so that the processing such as saving and restoring of the PC, PSW, and general-purpose register is not performed every time the capture performs the capture operation. , It is possible to reduce the time spent for unintended processing such as saving and restoring of PC, PSW, general-purpose registers, etc., which becomes a problem when the number of input channels increases, and improve the usage efficiency of the execution unit. When the number increases, it is possible to easily deal with a large number of input channels simply by setting the macro service channel, and it is not necessary to add an FRC or a capture register. Therefore, the amount of hardware used can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the panel interval measuring device of the present invention, and FIG. 2 is a pulse input device 60 in FIG.
0 and more detailed block diagram of the I / O request control unit 900, 3rd
FIG. 4 is a timing chart showing the operation of the pulse interval measuring device in the present embodiment, FIG. 4 is a block diagram of the pulse measuring device of the conventional example, and FIG. 5 is a flowchart of interrupt processing in the conventional example. 1 ... Channel, 2 ... Channel, 100 ... Microcomputer, 101 ... Execution section, 102 ... Program counter (PC), 103 ... Arithmetic and logic unit (ALU), 104 ... Program status word (PSW), 105 ... General purpose register, 106 ... Instruction register, 108 ... Execution control block, 150 ... I / O request receiving block, 200 ... Program memory, 300 ... Data memory, 301 ... Transfer area Pointer, 302 ... Data transfer area, 351 ... Capture value storage area, 361 ... Calculation result storage area, 381 ... Software flag area, 382 ... Software flag (for channel 1), 383 ... Software Flag (for channel 2), 391 ... Status save area, 400 ... Interrupt control unit, 401,402 ... Interrupt control line, 500 ... Pulse input device, 511,521 ... Free running counter (FRC), 51 2,522 …… Capture register, 531,532 …… Falling edge detection signal line, 540 …… Pulse control circuit, 600 …… Pulse input device, 611 …… Free running counter (FRC), 612… Capture register, 631 …… Rising Falling edge detection signal line, 632 ... Channel signal line, 633 ... Terminal level signal line, 640 ... Pulse control circuit, 700 ... Internal bus, 900 ... I / O request control unit, 910 ... Capture end I / O request signal line.

Continued Front Page (72) Inventor Shigeo Katori 5-33-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (56) Reference JP-A-60-183626 (JP, A)

Claims (4)

[Claims] 1. A program memory, a data memory, an I / O request receiving unit, an instruction executing unit, a program counter, and an execution unit including a program status word indicating an execution operation state, a counter for counting clocks, a cap register, and Receiving a first pulse signal and a second pulse signal, generating a detection signal each time a predetermined inversion edge appears in these pulse signals, and storing the contents of the counter at that time in the cap register,
Further, a pulse input device having a pulse control circuit for generating a level signal having a logic level based on the level of the pulse signal different from the pulse signal in which the predetermined inversion edge appears, the level of the inversion edge in the pulse signal,
An I / O request control unit that issues a processing request to the I / O request receiving unit of the execution unit in response to the detection signal;
The / O request accepting unit, based on the processing request, outputs the macro service processing code designating the first form when the level signal is the first logic level and the second when the level signal is the second logic level.
The macro service processing code designating the form of the above is given to the instruction executing means, and the instruction executing means prohibits the address update of the program counter and interrupts the execution of the program in response to the macro service processing code. In the state where the information of the program counter and the program status word at that time is kept as it is without being saved in the data memory, when the macro service processing code indicates the first form, the contents of the capture register are changed to the data. Data is transferred to a data transfer area in the memory, and when the second mode is shown, an operation is performed on the content of the data transfer area and the content of the capture register, and the content of the operation result is stored in the data in the data memory. Transfer to the transfer area and then execute the interrupted program Pulse interval measuring device, characterized in that to resume management. 2. The pulse control device further generates a channel signal indicating by a logic level of which of the first and second pulse signals the predetermined inversion edge appears, and the instruction execution. The pulse interval measuring device according to claim 1, wherein the means controls the sign of the result obtained by the calculation according to the logical level of the channel signal. 3. The instruction executing means has an ALU for executing the program, and executes an operation on the contents of the data transfer area and the contents of the capture register using the ALU. Claim 1 to
The pulse interval measuring device according to item 2 or item 2. 4. The pulse interval measuring device according to claim 3, wherein the arithmetic operation using the ALU is a subtraction process for subtracting the contents of the capture register from the contents of the data transfer area.