JPS63233455A - Microprocessor - Google Patents

Abstract

PURPOSE:To omit the change of a software in a system and the addition of an external circuit even in the case of connecting the peripheral I/O of slow access and to simplify a constitution by providing a general microprocessor with an external I/O access start/delay block. CONSTITUTION:When an access request (b) to the external peripheral I/O is outputted from an execution block 3 in the microprocessor, an event counter 2 starts counting, counts up its contents only by the value of a delay cycle value setting register 1 and outputs an external access request (c) to an external bus access block 4. Although the execution block 3 outputs a request to the event counter 2 only when external I/O access is required, the block 3 outputs an external memory access request directly to the block 4 based on a direct signal (f) in other cases. Thus, even if external I/O access are continued, the time up to the succeeding I/O access start can be delayed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a microprocessor.

[Conventional technology]

In conventional microprocessors, when accessing external memory or peripheral ICs (hereinafter referred to as external peripheral ICs), the microprocessor must when reading from or writing to.

It has a path waiting function that extends the access time by inputting a read control signal or a write control signal from an external signal or by setting it internally in the microprocessor.

[Problem that the invention seeks to solve]

The conventional microprocessor described above only has a path wait function that extends the access time when connecting an external low-speed access IO, so when continuously accessing the low-speed access IC, reading/writing to the low-speed access IC is difficult. Cycle time cannot be met. In order to prevent this, the software should add a dummy instruction between consecutive access instructions to increase the time.

For external devices, it is necessary to process the reliability using the circuit. At this time, the software method for dealing with this problem is that as the speed of microprocessors increases, the access cycle time becomes shorter, and it becomes necessary to change the dummy instruction each time, resulting in the loss of software inheritance. Furthermore, the method of dealing with the problem using an external circuit has the disadvantage that the system path is occupied for a long time, resulting in a decrease in system performance.

[Means for solving problems]

According to the present invention (-), in a microprocessor having a bus wait function that extends access time to an external peripheral IC, a predetermined external access delay cycle value is set at startup of the microprocessor, and software: a delay cycle value setting register whose cycle value can be changed, and the external peripheral I of the microprocessor that is activated by an external access request and until the set external access delay cycle value is counted.
A microprocessor is obtained, characterized in that it includes a means for delaying access to C.

〔Example〕

Next, nine aspects of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microprocessor (=added functions) of an embodiment of the present invention.A delay cycle value setting register 1 is set to a predetermined value when this microprocessor is started up, and then the program ( The event counter 2, which is a register whose value can be changed from 2 to 2, and which operates in response to the processor clock a, starts counting when there is an access request to the external peripheral IC from the execution block 3 of the microprocessor, and sets the delay cycle value. It counts the value of register 1 and issues an external access request C to external path/access block 4 (2). Also, event counter 2 is counted by the processor clock a. Due to external access request C, external work is 0
Lead signal d or external processing.

A write signal e is issued to the external peripheral IC.

The execution block 6 issues a request to the event counter 2 only when external memory access is required, and in response to an external memory access request, the external path access block 4 is directly sent a signal f without passing through the event counter 2. Make a memory access request.

Next, a specific operation flow will be explained using FIG. 1, FIG. 2, and FIG. 6. If the execution block 3 determines that it is an IO access command, it immediately issues a count start request to the event counter 2, that is, an access request.
The event counter 2 starts counting when the access request C rises, counts by the value of the delay cycle value setting register 1, and then raises the external access request C. At this time, if the delay cycle value is zero, the timing will be as shown in Figure 2, and if the delay cycle value is 1'', as shown in Figure 3, the timing will be one program from the rising timing of external access request C in Figure 2. External access request C due to set clock delay
stands up.

By setting the delay cycle value to 1 or more in this way, even in the case of software in which external IO accesses are executed continuously, the cycle time from the end of the first external IO access to the start of the next external IO access is A can be extended.

〔Effect of the invention〕

As explained above, the present invention provides a conventional general-purpose microprocessor with an external IO access start delay block, so that even when the microprocessor speeds up,
By setting or initializing the external access start delay cycle value when starting up the microprocessor.

Even when peripheral ICs with low-speed access are connected.

This has the effect that there is no need to change the system software or process the external 0 access signal using an external circuit.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the functions added to the microprocessor according to the present invention, and Figure 2 is a block diagram of the functions added in Figure 1. Timing diagram, Fig. 6 is a minimum timing diagram of the external operation access cycle when the delay cycle value = 1. Explanation of symbols: 1 is the delay cycle value setting register, 2 is the event counter, 6 is the execution block. 4 is the execution block. External path access block, a is the processor clock, b is the access request, C is the external access request, d is the external process 0 read signal, e is the external IQ write signal, and f is the direct signal. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A bus that extends access time to external peripheral ICs.
In a microprocessor with a wait function, a predetermined external access delay cycle value is set when the microprocessor is started up, and the delay cycle value can be changed by software. and means for delaying access of the microprocessor to the external peripheral IC until the set external access delay cycle value is counted.