JPH0632051B2 - Information processing equipment - Google Patents

Description

The present invention relates to an information processing apparatus having a pulse output device for controlling peripheral devices and the like.

[Conventional technology]

2. Description of the Related Art Today, microcomputers have been highly integrated due to the progress of LSI technology, and various kinds of peripheral hardware have been mounted on one chip. Among them, the pulse output device is indispensable for controlling external devices (hereinafter referred to as external devices) such as hydraulic pumps and motors, and the number of external devices to be controlled by the microcomputer is increasing. Are often provided with multiple channels.

The conventional technique will be described below with reference to FIGS. 4, 5, and 6. The microcomputer 020 is an execution unit 100 that reads and executes a program, a storage unit (hereinafter, referred to as a memory) 2 for storing the program and data.
00, an interrupt control unit 300 that receives an interrupt signal from each peripheral hardware and notifies the execution unit 100, a pulse generator 400 that generates an arbitrary pulse, and a peripheral bus 500 that transfers data of each unit. . The execution unit 100 includes a program counter 101 indicating an execution address of a program, a program status word (hereinafter PSW) 102 indicating a state of the execution unit 100, a general register 103, an arithmetic logic operation unit (hereinafter ALU) 107 for performing an arithmetic logic operation, and It has an instruction register 108 that stores an instruction code, and an execution control unit 109 that decodes the instruction code stored in the instruction register 108 and controls the execution of each unit. The memory 200 includes a program storage area 230 for storing a program, and a save area (hereinafter referred to as a save area) 240 for temporarily saving the program counter 101, PSW 102, and general register 103 when executing an interrupt program. The pulse generator 400 is a counter (hereinafter referred to as CN
T) 406, 407, CNT 406, 407 register (hereinafter, comparison register) 411, 421 performing comparison operation, CNT 406, 407 and comparison register 411, 421 match value, active (“1”)
Matching signal lines 414,424 and an output latch that inverts the output value when the matching signal lines 414,424 become active ("1")
It is composed of output signal lines 413 and 423 for outputting the values of 412 and 422. The interrupt request control unit 300 also includes a comparison register 41.
Execution unit 100 receives the interrupt request from 1,421.
Has an interrupt request signal line 310 for notifying the user. The interrupt control unit 300 also accepts interrupt request signal lines from other peripheral hardware, but this is omitted in this conventional example.

Next, the operation of each hardware will be described with reference to FIG. The CNTs 406 and 407 of the pulse generator 400 start counting after the system reset is released, and count up each time a count clock arrives. CNT406,4
When 07 performs the counting operation and becomes equal to the values of the comparison registers 411 and 421, the comparison registers 411 and 421 cause the match signal lines 414 and 421,
424 is activated (“1”). Match signal line 414,
424 is an interrupt request signal line to the interrupt control unit 300 as it is. The CNTs 406 and 407 are the same signal lines 4
When 14,424 becomes active, it is cleared to 0 and the counting operation is performed again from 0. The output latches 412, 422 are reset by the system reset and have the output value "0". After releasing the system reset, the output values of the output latches 412 and 422 are inverted each time the FRC 405 and the comparison registers 411 and 421 match and the comparison registers 411 and 421 activate the match signal lines 414 and 424 (“1”). The values of the output latches 412 and 422 can be read by software.
The interrupt request control unit 300, when the coincidence signal lines 414 and 424 become active (“1”), the interrupt request signal line 310.
Is made active (“1”) and the execution unit 100 is requested to perform interrupt processing. The execution unit 100 reads an instruction from the program storage area 230 on the normal memory 200 according to the program counter 101 and stores it in the instruction register 108, and the execution control unit 109 decodes the instruction code of the instruction register 108 and executes the instruction. Execution unit 100
Detects the interrupt request signal line 310 every time the execution process of one instruction is completed and is inactive (“0”), the above instruction execution operation is repeated. After the execution unit 100 finishes one instruction, if the interrupt request signal line 310 is detected and the interrupt request signal line 310 is active (“1”), the interrupt process described below is executed. When the interrupt request signal line 310 becomes active (“1”), the execution unit 10
Since 0 holds the execution state of the program currently being executed, the values of the program counter 101, PSW 102, and general register 103 are sequentially stored in the save area 240 on the memory 200. After the above processing, the execution unit 100 starts executing the interrupt processing program.

Next, the processing contents of the interrupt processing will be described with reference to the flowchart of FIG. 5 and the timing chart of FIG.
In the interrupt processing program, the execution unit 100 first reads the value of the output latch 412. The execution unit 100 calculates the low level width when the value of the output latch 412 is "0", and calculates the high level width when the value of the output latch 412 is "1". At t0, the value of the output latch 412 becomes “1”, so the interrupt program started at t0 calculates the pulse width T ₁ to be output next. Next, the execution unit 100 transfers the pulse output width T1 to the comparison register 411. After the above processing, the program counter 101, PSW 102, and general-purpose register 103 are restored from the save area 240.

Through the above processing, the comparison register 411 activates the coincidence signal line 414 at the timing of t1 to restart the above interrupt processing.

Through the processing described above, the pulse output device 400 outputs a pulse from the output signal line 413. Further, here, the interrupt processing regarding the comparison register 411 and the output latch 412 has been described, but the comparison register 421 and the output latch 41 are described.
The same process is applied to the item 2.

[Problems to be solved by the invention]

(1) Since the conventional pulse output device processes and processes the output pulse data by executing the interrupt program, the PC, PSW, and general-purpose registers are saved at each output change timing, and after the interrupt processing , Again PC, P
Since processing such as SW restoration is required, during the actual execution time required for the entire interrupt processing, the status save and restore processing time is longer than the processing time of the execution section required for the interrupt processing itself. The processing efficiency is poor.

(2) The processing efficiency of the execution unit described above further deteriorates as the output pulse data of the pulse output device increases and the number of channels increases.

(3) Since the conventional pulse output device has a configuration in which each channel has one counter and one comparison register, an enormous increase in hardware is required when the number of channels is increased.

[Means for solving problems]

According to the present invention, a central processing unit, a storage unit for storing data, and a pulse output unit are integrated on a single semiconductor substrate, and in the information processing unit, the central processing unit outputs the pulse from the storage unit while holding the execution state of the program. A data transfer means for transferring data to the device is provided.

[Embodiment] Next, FIG. 1, FIG. 2 and FIG.
It will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention in which a microcomputer 010 includes an execution unit 100 for reading and executing a program, a storage unit (hereinafter referred to as a memory) 200 for storing the program and data, and a peripheral hardware. Execution unit 10 that receives an interrupt signal
Interrupt control unit for notifying 0 (hereinafter I / O request control unit)
305, a pulse generator 400 for generating an arbitrary pulse, and a peripheral pulse 5 for passing data between respective parts.
It consists of 00. The execution unit 100 includes a program counter 101 that indicates an execution address of a program and an execution unit 10.
PSW102 general-purpose register 103 indicating 0 state, ALU 107 performing arithmetic logic operation, instruction register 108 storing instruction code, execution control unit 1 decoding instruction code stored in instruction register 108 and controlling execution of each unit
09, the I / O request control unit 305 has an acknowledge signal line 325 for indicating that the I / O request is received. The memory 200 includes a program storage area 230 for storing programs, buffer memories 210, 220 for storing output pulse data of the pulse generator, and buffer memories 210, 2
It comprises transfer count storage areas 280 and 290 for storing the data transfer count of 20 and memory pointers 285 and 295 pointing to the head addresses of the buffer memories 210 and 220. The pulse generator 400 is a register (hereinafter, comparison register) 411, 421, FR that performs a comparison operation with a free-running counter (hereinafter, FRC) 450, FRC405 that counts the count clock φ.
When the values of C405 and the comparison registers 411 and 421 match, the match signal lines 414 and 424 that become active (“1”) and the output values of the output latches 412 and 422 and the output latches 412 and 422 that invert the output value when the match signal lines 414 and 424 become active are output. Output signal lines 413 and 423. The I / O request control unit 305 indicates that the I / O request is activated by the activation of the match signal lines 414 and 424.
An I / O request signal 315 for notifying the user and an I / O request processing code generation circuit 308 for generating a processing code for processing the I / O request.

In the present embodiment, the execution unit 100 program counter 1
01, PSW102, general register 103 is not saved,
I / O request processing is performed while maintaining the state of the execution unit 100. (Hereinafter, this processing form is referred to as a macro service.) Next, the operation of each peripheral hardware will be described with reference to FIG. The FRC 405 of the pulse output control unit 400 starts the counting operation after the system reset is released, and the count clock φ
Count up every time. When the FRC 405 performs the counting operation and becomes equal to the values of the comparison registers 411 and 421, the comparison registers 411 and 421 activate the coincidence signal lines 414 and 424 (“1”). Matching signals 414 and 424 are I /
It becomes an I / O request signal to the O request control unit 305. The output latches 412 and 422 are reset by the system reset and have the output value "0". After releasing the system reset, the output latches 412 and 422 invert the output value every time the comparison registers 411 and 421 activate the coincidence signals 414 and 424. I /
The O request control unit 305 activates the I / O request signal line 315 (“1”) when the match signal lines 414 and 424 become active, and notifies the execution unit 100 that an I / O request has been issued. Also, the I / O request control unit 305
When the execution unit 100 activates the acknowledge signal 325, the I / O request processing code generation circuit 308 outputs the I / O request processing code to the peripheral bus 500. The execution unit 100 stores the program in the normal program memory 230 in the read instruction register 108, and the execution control unit 1
09 decodes the value of the instruction register 108 and executes it. The execution unit 100 detects the I / O request signal line 315 every time the execution of one instruction is completed, and repeats the above instruction execution operation if it is inactive (“0”). After the execution unit 100 finishes executing the instruction, the I / O request signal line 315
Is detected and the I / O request signal line 315 is active (“1”), the processing of the program being executed is temporarily suspended, and the buffer memories 210 and 220 change the comparison register 411,
The macro service processing for transferring to 421 is performed.

Next, with reference to FIG. 1, the I / O request processing and the operation of the pulse output device in this embodiment will be described. Execution unit 10
For 0, the program in the program storage area 230 is read and stored in the instruction register 108 until the I / O request signal line 315 becomes active (“1”), and the execution control unit 1
09 decodes the content of the instruction register 108 and executes it. The program counter 101 in the execution unit 100 points to the address of the instruction to be executed next, and PSW1
Reference numeral 02 indicates the state of the execution unit 100 according to the program currently being executed, and the general-purpose register 103 stores data being processed. When the I / O request signal line 315 becomes active (“1”), the execution unit 100 causes the buffer memories 210, 2
Macro service processing for transferring data from 20 to the comparison registers 411 and 421 is performed. When the I / O request signal line 315 becomes active (“1”), the execution unit 100 makes the acknowledge signal 325 active (“1”) and causes the I / O request processing code generation circuit 308 to transfer the processing code of the transfer process. Is output to the peripheral bus 500. Execution control unit 109
Writes the processing code of this transfer processing directly to the instruction register 108, and holds the program counter 101, PSW 102, and general-purpose register 103 while holding the buffer memories 210 and 220.
To the comparison registers 411 and 421 is executed.

Upon receiving the above I / O request, the execution unit 100 executes the following processing.

(1) Memory pointer 2 that indicates the buffer memory address
AL values 85,295 and transfer circuit storage areas 280,290
U107 is used for addition, transfer data is read from the transfer data address obtained by the addition, and pulse generator 4
It transfers to the comparison register 411,421 in 00.

(2) After the transfer processing, the execution unit 100 displays the transfer count storage area 2
Decrement the value of 80,290 using ALU107. If the decrement result is not "0", the execution of the program executed before the I / O request processing is restarted. If the decrement result is "0", the execution unit 100
Activates a data transfer completion interrupt request for the buffer memories 210 and 220.

Through the above processing, the program counter 10 of the execution unit 100
The transfer operation from the buffer memories 210 and 220 to the comparison registers 411 and 421 can be performed without saving and restoring the PSW 102 and the general-purpose register 103.

Next, referring to FIGS. 2 and 3, the buffer memory 210
The relationship between the value set in the above and the pulse output from the output signal line 413 will be described. In FIG. 2, the buffer memory 21
0 has pulse data 211 to 217, and the memory 200 additionally has a transfer count storage area 280 and a memory pointer 285. The addresses of the pulse data 211 to 217 are set to increase from the pulse data 217 to the pulse data 211, and the pulse data 211 to 217 are set to the values t1 to t7.

In the initial state, the value of the transfer count storage area 280 indicates the number of pulse data, and the memory pointer 285 points to the pulse data 217. The initial value t0 is set in the comparison register 411. In this state, when the values of the FRC 405 and the comparison register 411 match at the timing of t0 to activate the match signal line 414 and activate the I / O request processing, the execution unit 100 causes the execution unit 100 to store the memory pointer 285 and the transfer count storage area 280. Pulse data 211
Calculate the address of. Based on this address information, the value t1 of the pulse data 211 is transferred to the comparison register 411. Subsequently, the execution unit 100 determines the transfer count storage area 280.
Decrement the value of. At the timing t0 when the coincidence signal line 414 becomes active, the output latch 412
Inverts the output value.

Next, at the timing of t1, the FRC 405 and the comparison register 411
Match, the match signal line 414 is activated, and I /
When the O request process is activated, the execution control unit 109 again adds the values of the memory pointer 285 and the transfer count storage area 280. The addition result indicates the address of the pulse data 212, and the execution control unit 109 transfers the value of the pulse data 2122 to the comparison register 411 based on the address. Similarly, the pulse data 213, 214, 215, 216, 217 values are t2,
Transfer to the comparison register 411 at the timing of t3, t4, t5, t6.

The value of the timing transfer count storage area 280 at t7 when all the pulse data on the buffer memory 210 has been transferred becomes 0, and the transfer completion interrupt process is activated. A series of pulse data can be output again by updating the pulse data 211 to 217 by this transfer completion interrupt process. Further, the pulse data on the buffer memory 220 can be output by performing the same processing on the buffer memory 220 and the comparison register 421.

〔The invention's effect〕

As described above, according to the present invention, every time the pulse output device outputs the coincidence signal, the value of the buffer memory on the memory is changed by the process of directly writing the transfer process instruction to the instruction register while keeping the state of the execution unit. The following effects can be obtained by performing the transfer processing to the comparison register.

(1) Since the present invention does not process the transfer of pulse train data by executing the interrupt program, the PC, PSW, and general-purpose registers are saved at each output change timing,
After interrupt processing, there is no need to perform processing such as restoring PC and PSW again. Therefore, compared with the conventional pulse output device that transfers data by interrupt processing, the processing time of saving and restoring the status is not included in the execution time actually required for the entire interrupt processing, so that the processing efficiency of the execution unit is extremely high. high.

(2) In the case of a normal pulse output device, the processing efficiency of the above execution unit increases as the pulse output data increases, and the time required to save and restore the program counter, PSW, and general-purpose registers increases as the number of channels increases. Although the processing capacity of the execution unit decreases, the pulse output device of the present invention does not decrease the processing efficiency with the number of channels.

(3) Since the pulse output device of the present invention is composed of one FRC and the comparison register for each channel, even if the number of channels of the pulse output device is increased, it can be dealt with only by adding the comparison register.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a buffer memory 210, and FIG. 3 is a pulse output device 4
00 is a pulse output waveform diagram, FIG. 4 is a block diagram of a conventional example, FIG. 5 is a flowchart showing interrupt processing of the conventional example, and FIG. 6 is a pulse output waveform diagram of the pulse output device 400. 010,020 ... Microcomputer, 100 ... Execution unit, 101 ... Program counter, 102 ... PS
W, 103 ... General-purpose register, 107 ... ALU, 10
8 ... Instruction register, 109 ... Execution control unit, 300 ...
… Memory, 210,220 …… Buffer memory, 211,21
7 ... Pulse output data, 230 ... Program memory, 240 ... Save area, 280,290 ... Transfer count storage area, 285,295 ... Memory pointer, 300 ... Interrupt control section, 305 ... I / O request control section, 308 …… I /
O request processing code generation circuit, 310 ... Interrupt request signal line, 315 ... I / O request signal line, 325 ... Acknowledge signal line, 400 ... Pulse output device, 405 ...
FRC, 406 ... Counter, 407 ... Counter, 4
11,421 ... Comparison register, 412,422 ... Output latch, 413,423 ... Output signal line, 414,424 ... Match signal line,
500 …… Peripheral bus.

Claims (1)

[Claims] 1. A central processing unit that executes a program, a storage unit that stores count comparison data, a counter that counts clock signals, and a coincidence signal is generated when the count value of this counter matches a set value, and the central unit. A pulse output device having a comparison means for issuing a processing request to the processing device and an output means for outputting a pulse based on the coincidence signal, wherein the central processing unit responds to the processing request from the comparison means. The information processing apparatus further comprising: a data transfer unit that temporarily suspends the execution of the program and transfers the count comparison data as the set value from the storage unit to the comparison unit while maintaining the execution state of the program at that time.