JPH0752395B2 - Information processing equipment - Google Patents

Description

The present invention relates to a pulse generator for controlling peripheral equipment.

[Prior Art] A pulse output device is widely used for controlling an air conditioner and other devices by a three-phase AC motor.

Fig. 3 shows 3-phase PWM (pulse width modulation) from pulse output U, V, W
FIG. 6 shows a pulse timing diagram for obtaining a signal.

The conventional technique will be described with reference to FIGS. 5 and 6.
Figure 5 shows the central processing unit (hereafter CPU) 000A, interrupt request generation circuit (hereafter INTC) 100A, peripheral hardware 200A, memory
It consists of 300A and data bus 400A. The CPU000A includes a program counter (hereinafter PC) 001A, a program status word (PSW) 002A, a general-purpose register 003A, an arithmetic logic unit (ALU) 004A, an instruction register 005A, and an execution control unit 006A. Peripheral hardware 200A is IN
The interrupt signal 201A is output to the TC100A, the INTC100A determines the priority of these interrupt signals, and outputs an interrupt request signal to the execution control unit 006A of the CPU000A.

Figure 6 shows a free-running counter (FRC) 61 that counts the count clock inside the peripheral hardware.
And a compare register 62, an output port register 65, an output port 66, and a buffer register 64 that transfers data to the output port register 65 by a match signal 63 from the compare register 62. The match signal line 63 remains as it is in the INTC100A.
It becomes an interrupt signal to.

The operation will be described below with reference to FIG. The data written in the output port register 65 is directly output to the output port 66. Of the output pulses output from the output port 66, the compare register 62 is set to the change timing time of the port in which the data changes first,
It will be explained from the point where the match signal from the compare register 62 is generated.

First, by the coincidence signal 63, the data in the buffer memory 64 is transferred to the output port register 65, and the transferred data is output from the output port 66.

On the other hand, the match signal 63 is an interrupt signal for the INTC100A, and the INTC100A is based on this interrupt, and the CPU000A
The interrupt request signal is output to the execution control unit 006A. CPU0
00A activates normal interrupt processing based on the interrupt request signal. That is, the program executed by the CPU000A is interrupted, the values of the PC001A, PSW002A, and the general-purpose register 003A are temporarily saved in the data memory 302A, and then the interrupt process is performed.

In the interrupt processing program, the data of the next change time of the output pulse output from the output port 66 is written in the compare register 62, and the value of the output pulse is written in the buffer register 64.

As described above, a pulse output can be obtained by activating the interrupt process each time the coincidence signal 63 becomes active (“1”) and updating the timing data and the output pulse data. Therefore, in order to obtain a three-phase PWM signal as shown in FIG. 3, the description will be made with reference to FIG. 4. First, as an initial value, T ₁ is set to the compare register 62 in the buffer register 64.
Set 06H to. Here, in order to make it easier to understand, the buffer register 64 and the output port register 65 are set to 8 bits, and the lower 3 bits, that is, U, V, W in the 2nd, 1st and 0th bits.
Allocate. Also, 07H is confirmed as the initial value in the output port register 65. Now, after the count operation starts, t ₁
After the first time, the first match signal appears and the output port register 65
Write 06H. Then, the interrupt process is activated, and T ₂ is set in the compare register 62 and 02H is set in the buffer register 64. Then, t ₂ hours after the first match signal is output, the next one-value signal is output, the output port register 65 is rewritten, and interrupt processing is activated to set the next match signal timing and the value of the buffer register 64. By repeating the above process, a three-phase PWM signal as shown in FIG. 3 can be obtained.

[Problems to be Solved by the Invention]

In the conventional pulse output device, the next change timing and the data train of the output pulse are set by the interrupt process each time the compare register is matched, but the PC, PSW, and general-purpose register are saved each time the interrupt process is performed. -Since processing such as restoration is involved, the efficiency of the execution unit is reduced due to processing other than the processing originally required.

In addition, it is theoretically difficult to obtain a higher-frequency PWM signal because it is necessary to always perform interrupt processing between the changing points of the pulse output.

[Means for Solving the Problems]

The present invention includes a CPU, a program memory, a data memory,
In a processing device having an INTC for asynchronously generating a processing request to the CPU and a peripheral circuit, the peripheral circuit responds to a match signal from a free running timer, a plurality of compare registers, and the plurality of compare registers. And a plurality of buffer registers for transferring data, a port register for receiving the data sent from the buffer register, and an output port for outputting the contents of the port register, and the central processing in response to the processing request. The device interrupts the execution of the program, transfers the data set in advance in the storage means to the compare register and the buffer register without saving the information indicating the state at that time to another area, and then interrupts the execution. It has the feature of executing program processing.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

1 and 2 show an embodiment of the present invention, and FIG. 1 shows CPU00.
0, INTC100, peripheral hardware 200, memory 300, data bus
It consists of 400. The CPU000 is composed of PC001, PSW002, general-purpose register 003, ALU004, instruction register 005, and execution control unit 006. The peripheral hardware 200 outputs a plurality of interrupt signals 201, ... To the INTC100, and the INTC100 judges the priority of these interrupt signals and the processing form, and the CPU0
The interrupt request signal 101 and the form instruction signal 102 are output to 00.

Fig. 2 is a block diagram of the pulse generation part included in the peripheral hardware 200. FR that counts the count clock.
C21 and a plurality of compare registers 22a, 22b, 22c, 22d ..., Output port register 25, output port 26, compare register 22
Data is transferred to the output port register 25 by the coincidence signals 23a, 23b, 23c, 23d, ... From a, 22b, 22c, 22d.

.., and the coincidence signals 23a, 23b, 23c, 23d ... Are directly interrupt signals to the INTC100.

The operation will be described below with reference to FIG. Output port
At 26, the data written in the output port register 25 is output as it is. Compare registers 22a, 22b, 22c, 22d,
... include buffer registers 24a, 24b,
The timing for transferring the data of 24c and 24d to the output port register 25 is set in advance. Also, buffer registers 24a, 24
b, 24c, 24d ... include compare registers 22a, 22b, 22c, 22d,
The output pulse data transferred to the output port register 25 by the coincidence signals 23a, 23b, 23c, 23d, ...

Now, the data of the buffer register 24a is written in the output port register 25 by the match signal 23a from the compare register 22a, and is output from the port 26. At this time, since the match signal 23a does not go to the INTC as an interrupt signal,
No interrupt processing is performed.

Then, the match signal 23b from the compare register 22b transfers the data in the buffer register 24b to the output port register 25 and outputs it from the port 26. At this time, the match signal 23b
Is sent as an interrupt signal to INTC.

In response to the request from the match signal 23b, the INTC100 sends a data processing request form instruction, which is different from the normal interrupt processing, to the CPU0.
Set in advance to set to 00.

The CPU 000 can process the interrupt request from the INTC 100 in two forms by the data processing form instruction signal 102. One is normal interrupt processing that involves processing such as saving and restoring the values of PC001, PSW002, and general-purpose register 003.
The other is to save the values of PC001, PSW002, general register 003,
This is a predetermined data process that is executed based on the process form information preset in a specific address in the data memory 302 without performing a process such as a return. Hereinafter, this predetermined data processing will be referred to as a macro service.

The processing form of the macro service is determined by the processing form information preset in the specific address in the data memory 302.

Now, by the interrupt signal by the match signal 23b, INTC100
Outputs macro service interrupt request signals 101 and 102 to CPU000. By specifying in advance to transfer the data set by the processing mode information to the compare registers 22a, 22b and the buffer registers 24a, 24b to the processing mode information corresponding to the macro service request by the match signal 23b, Buffer register 24a, 24b and buffer register 24 which are pulse output data each time signal 23b is output.
The data in the compare registers 22a, 22b for setting the timing of transferring a, 24b to the output port register 25 is updated.

22c and 22d, 22e and 22f for the remaining compare registers
Pairs of two are paired with each other, and the match signals 23d, 23
Each time f, ... Is output, the macro service processing transfers the data designated by the processing mode information to the paired compare register and the corresponding buffer register.

As described above, according to the match signals 23a, 23b, 23c ... Of the plurality of compare registers 22a, 22b, 22c ..., the data of the corresponding buffer registers 24a, 24b, 24c ,.
To output a pulse from multiple output ports 26, and activate the macro service process by the match signal output from a specific compare register, and prepare the data prepared in advance in the compare register and buffer register specified in advance. By transferring the data, a pulse generator for updating the timing data and the output pulse data can be obtained.

For example, the case of obtaining the PWM output as shown in FIG. 3 will be described with reference to FIGS. 2 and 4. Now compare registers 22a, 22b,
It is assumed that there are four sets of 22c, 22d buffer registers 24a, 24b, 24c, 24d, and the lower 3 bits of the buffer register and the output port latch correspond to U, V, W. To the initial value, compare registers 22a, 22b, 22c, 22d with T ₁ ,
The _{T 2, T 3, T 4} , also buffer register 24a, 24b, 24c, the 24d sets 06H, 02H, 00H, and 02H. After ₁ hour t, 06H is first written to the output port register 25. At this time, the compare register 22a and the buffer register 24a are not updated by interrupt processing or the like. Further, t ₂ hours later, the match signal 23b is output from the compare register 22b, and 02H is written in the output port register 25 from the buffer register 24b. At this time, the macro service process is activated, and the values of the compare registers 22a, 22b and the buffer registers 24a, 24b are rewritten to T ₅ , T ₆ , 06H, 07H, respectively. This rewriting is t
_It suffices that this is done by ₃ + t ₄ + t ₅ hours later, during which the pulse output can be controlled by the compare registers 22c and 22d. The desired pulse output can be obtained by repeating such operations thereafter.

〔The invention's effect〕

As described above, the present invention controls a plurality of output ports at a time by transferring the value of the buffer register to the output port register by the match signal of the compare register, and the number of the compare register and the buffer register is increased. By having a pair, it is not necessary to update the data by interrupt processing each time a compare register match occurs, and by updating the compare register and buffer register data by macro service processing, PC, PSW, general-purpose CPU time is not saved for processing such as register saving and restoring.

Therefore, it is possible to obtain high-frequency PWM output while saving sufficient CPU time for main processing.

[Brief description of drawings]

FIG. 1 is a configuration diagram of peripheral hardware in one embodiment of the present invention, FIG. 2 is a system configuration example in the present invention,
FIG. 3 is a timing diagram of a three-phase AC signal, and FIG.
FIG. 5 is a partially enlarged view of the figure, FIG. 5 is a conventional peripheral hardware configuration diagram, and FIG. 6 is a conventional system configuration diagram. 11,31 …… Free running timer, 12a, 12b, 12c, ..., 32
...... Compare register, 13a, 13b, 13c, ..., 33 …… Match signal, 14a, 14b, 14c, ..., 34 …… Buffer register, 15,35…
… Output port register, 16,36 …… Output port, 101,10
1 '... Interrupt request signal, 102 ... Form designation signal.

Claims (1)

[Claims] 1. A central processing unit, a storage means for storing programs and data, a peripheral circuit, and asynchronously generate a processing request to the central processing unit in response to a plurality of interrupt requests output from the peripheral circuit. In an information processing device having an interrupt request generation circuit, the peripheral circuit includes a free running counter, a plurality of comparison registers, and a plurality of buffers for transmitting data in response to respective match signals from the plurality of comparison registers. A register, a port register for receiving the data sent from the buffer register, and an output port for outputting the contents of the port register, and the plurality of comparison registers are composed of at least two or more comparison registers. It is classified into the above multiple groups, and from a certain comparison register in each group Has a means for generating a processing request to the central processing unit via the interrupt request circuit in response to a coincidence signal input thereto, and the central processing unit suspends execution of the program in response to the processing request. , All the comparison registers in the group to which the comparison register, which has caused the processing request, is stored in the storage unit without saving the information indicating the state at that time to another area, An information processing apparatus comprising means for executing a suspended program processing after transferring to all the buffer registers corresponding to each comparison register.