JPH0378661B2 - - Google Patents

Description

[Detailed description of the invention] 〔table of contents〕 The present invention will be explained in the following order.

A. Overview B. Field of industrial application C. Conventional technology (Fig. 4, Fig. 5) D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example ( (Fig. 1, Fig. 2, Fig. 3) G1 Explanation of DMA controller (Fig. 2) G2 Explanation of data chain operation (Fig. 3) H Effect of the invention A [Summary] A data chain method in DMA transfer. , even if the setting of the chaining register is not completed in time at the end of one data transfer, the transfer is not terminated, the response to the DMA transfer request is delayed, and the data transfer is resumed after resetting the subchannel.

B [Field of Industrial Application] The present invention relates to a data chain method in which input/output operations are performed continuously between an input/output device and multiple areas in main memory in DMA transfer, and more particularly,
(Direct Memory Access) The controller is equipped with a subchannel register that controls the input/output operation being executed and a chaining register that stores information that controls the next input/output operation. At the end, information is copied from the chaining register to the subchannel register so that input/output operations between the input/output device and multiple areas in main memory are performed continuously.
Concerning data chain method in DMA transfer.

In a computer system, a method in which input/output operations are performed continuously between an input/output device and multiple areas in main memory is called a data chain method. In this data chain method, when the data transfer for one area is completed, the channel processor receives an interrupt, reads the instruction for the next data transfer, resets it in the data transfer control register, and then transfers the next data. Writes the transfer method and control information for the next data transfer to the chaining register while data transfer is in progress, and copies the control information in the chaining register to the subchannel register for data transfer control when the data transfer is complete. There is a method in which the next data transfer is performed. The present invention relates to the latter data chain method.

C [Prior Art] FIG. 4 is a block diagram showing the configuration of a data chain method in conventional DMA transfer.

In FIG. 4, 11 is a main memory, and 12 is a central processing unit. Reference numeral 13 denotes an input/output device (IO), and the figure shows two input/output devices 13A and 13B as an example. Reference numeral 14 denotes an input/output device controller (IO controller), which includes an internal buffer (not shown) and controls data transfer between the input and output devices. The figure shows IO controllers 14A and 14B for input/output devices 13A and 13B. 15 is a channel mechanism with a channel inside.
It is equipped with a processor (CHP) 16 and a DMA controller 17. CHP16 decodes instructions and
IO controller 14 and DMA controller 17
control. The DMA controller 17 has a subchannel 1 that controls input/output operations being executed internally.
8 and a chaining register 19 into which control information for controlling the next input/output operation is written, and executes data transfer between the main memory 11 and the IO controller 14.

Next, the continuous data transfer method between the main memory 11 and the input/output device 13 using the data chain method shown in FIG. Fifth
This will be explained using figures.

In FIG. 5, a in the upper row indicates the operation timing of the CHP 16, and the CHP 16 simultaneously processes processing 1, processing 2, and chain processing for the IO controller 14A in a time-sharing manner. Processing 1 has the highest priority, followed by chain processing and processing 2. b in the middle row shows the timing of data transfer operation between the main memory 11 and the IO controller 14A, and c in the lower row shows the timing of the data transfer operation between the IO controller 14A and the input/output device 13A.

The data transferred from the main memory 11 is temporarily stored in a buffer (not shown) of the IO controller 14A, and then sent to the input/output device 13A. Therefore, the transfer between the main memory 11 and the IO controller 14A is performed between the IO controller 14A and the input/output device 13.
As shown in b and c, the transfer between A and A can be performed in advance by the number of buffer stages.

When transfer 1 between the main memory 11 and the IO controller 14A is completed, control information for transfer 2 is stored in the chaining register 19 in the DMA controller 17, so after this is copied to the register in the subchannel 18, ,CHP
An interrupt is made to 16.

According to the control information for the transfer 2, the transfer 2 is performed between the main memory 11 and the IO controller 14A following the transfer 1, as shown in b.

On the other hand, when the CHP 16 receives an interrupt from the DMA controller 17, it is performing the low-ranking process 2, so it immediately accepts the interrupt and transfers the control for transfer 3 to the chaining register 19 in the DMA controller 17, as shown in a. Configure information.

Transfer 2 between the main memory 11 and the IO controller 14A is completed and the DMA controller 17 transfers to the CHP 16.
When the interrupt request is made, the CHP 16 is executing process 1, which is higher in rank than the chain process, so the setting of control information for the next transfer 4 to the chaining register 19 is suspended. Further, even when transfer 3 is completed between the main memory 11 and the IO controller 14A, the CHP 16 is still executing process 1, so the control information for the next transfer 4 is not set. If the chaining register 19 is not set in time and chaining is not possible when the transfer 3 being executed by the subchannel 18 ends, the DMA controller 17 notifies the IO 13A of the end of the transfer.

When the process 1 is completed, the CHP 16 restarts the IO controller 14A and resumes the process after the next transfer 4.

D [Problems to be Solved by the Invention] As mentioned above, in the conventional data chain method, the chaining registers were not set in time, and chaining was not possible when the subchannel finished the input/output operation in progress. In this case, the input/output device is notified of the end of the transfer, and when it becomes ready for transfer,
The input/output device was restarted. In that case, there was a problem in that extra overhead was generated to restart the input/output device later.

In particular, the input/output device side is equipped with a buffer to temporarily store input/output data, and as shown in Figure 4 b and c, there is a delay in chain processing responses to transfer requests generated by the DMA controller. In the case of a system that can perform data transfer operations even if the amount increases to a certain extent, there is a problem that the buffer cannot be used effectively.

The present invention was made in order to solve the above-mentioned problems in the conventional data chain method, and there is a case where the chaining register cannot be set in time and chaining cannot be performed when the subchannel finishes the input/output operation in progress. Another object of the present invention is to provide a data chain system that allows input/output operations to continue without completing input/output operations and restarting them.

E [Means for Solving the Problems] FIG. 1 is a block diagram showing the configuration of the data chain system of the present invention.

Reference numeral 11 denotes a main memory, which includes a plurality of areas for performing data input/output operations with input/output devices. 12 is a central processing unit that performs information processing with the main memory 11 or the input/output device. Reference numeral 13 indicates input/output devices (IO), and four (13 ₀ to 13 ₃ ) are illustrated. Reference numeral 14 denotes an input/output device controller (IO controller), which is provided in four pieces (14 ₀ to 14 ₃ ) corresponding to each input/output device 13 ₀ to 13 ₃ and controls data transfer between each input/output device. . 15 is a channel mechanism with a channel processor (CHP) inside.
16 and a DMA controller 20.
The CHP 16 decodes instructions and controls the IO controller 14 and DMA controller 20. DMA
The controller 20 internally includes a subchannel 26 that controls the input/output operation being executed, a register 32 that indicates whether or not this subchannel is operable, and a chaining register 21 in which control information that controls the next input/output operation is set. It is provided with a register 25 that indicates whether or not the control information of the chaining register 21 can be used, and a determination circuit 36. If the control information in the chaining register 21 is unavailable when data chaining is to be performed, the determination circuit 36 displays on the register 32 that the subchannel 26 is inoperable and responds to subsequent DMA transfer requests. and CHP16 to indicate that chain processing is on hold.
to notify. Subchannel 26 is CHP16,
When the subchannel register 27 is reset and the register 32 indicates that the subchannel 26 is operational, the DMA transfer is restarted.

F [Function] During normal data chain operation, the main memory 11 and IO controller 1 that are being executed by the subchannel 26
Control information for the next input/output operation (transfer 2) after the input/output operation (transfer 1) between 4 is set in the chaining register 21. When transfer 1 is finished,
Transfer 2 set in chaining register 21
Control information for subchannel register 27
, and subchannel 26 performs transfer 2. At the same time, an interrupt is made to CHP16,
Control information for the next transfer 3 is set in the chaining register 21, and this operation is repeated thereafter.

If the control information in the chaining register 21 is unavailable when data chaining is to be performed after the transfer is completed, the determination circuit 36 determines that the subchannel 26 is inoperable.
is displayed so that responses to subsequent DMA transfers are suspended, and the CHP 16 is notified that chain processing is suspended. However, no notification of the end of the transfer is given.

When it is the turn to perform chain processing, the CHP 16 resets the control information for the next transfer in the subchannel register 27 and displays in the register 32 that the subchannel 26 is operational. When this indication occurs, subchannel 26 resumes DMA transfer.

As a result, even if the chaining register 21 is not set in time and chaining is not possible when the subchannel 26 finishes the input/output operation being executed, the response to the DMA transfer is delayed, and the input/output operation is finished and restarted. Input/output operations can be resumed continuously without performing startup processing.

G [Example] An example of the present invention will be described in detail with reference to FIGS. 1 to 3.

Figure 1 is a block explanatory diagram of the configuration of the present invention already explained, and Figure 2 is used in the present invention.
FIG. 3, which is an explanatory diagram of one embodiment of the DMA controller 20, is a timing chart illustrating the operation of one embodiment of the present invention.

G ₁ (Description of DMA Controller) In the DMA controller 20 in FIG.
21 is a chaining register, which is prepared for one subchannel, and a chain address register 22 in which a main memory address is stored.
, a chain byte counter 23 that indicates the number of bytes of data to be transferred, and a chain mode register 24 that stores transfer control information such as a data transfer direction and a chain flag.

25 is a valid flag/identification code register (VF/ID register), which contains a valid flag (VF) indicating whether the contents of the chaining register 21 are valid or not, and an identification code (VF) indicating which subchannel it is used for. ID)
is stored.

26 is a subchannel, which has four subchannels (26 ₀ to 26 ₃₎ and has corresponding input/output devices.
Controls input/output operations between main memories. 27 (27
₀ to 27 ₃ ) are subchannel registers, which are provided in each subchannel (26 ₀ to 26 ₃ ), and each have an address register 28 (28 ₀ to 28 ₃ ) that stores a main memory address therein, and data to be transferred. byte counter 2 indicating the number of bytes in
9 (29 ₀ to 29 ₃ ) and a status register 30 (30 ₀ to 30 ₃ ) that stores error information.
and a mode register 31 that stores transfer control information such as data transfer direction and chain flag.
(31 ₀ to 31 ₃ ).

32 is a ready flag register, and there are four (3) ready flag registers corresponding to each subchannel (26 ₀ to 26 ₃ ).
2 ₀ to 32 ₃ ), each having a ready flag (RF) indicating whether the corresponding subchannel is operational.

33 is an update circuit that updates the contents of the address register 28 and byte counter 29 in the subchannel register 27 every time data is transferred, and sets the error information in the status register 30 when error information is added. do.

34 is a chain status register;
It has a chain completion flag (CF) that is set when chain processing is completed, and a chain suspension flag (PF) that is set when chain processing is suspended. 35 is a multiplexer (MPX).

36 is a determination circuit that generates various control signals based on information from the VF/ID register 25 and the subchannel register 27 (the contents of which will be explained in detail in the following operation description).

With the above configuration, the DMA controller 20
With four subchannels (26 ₀ to 26 ₃ ), it is possible to simultaneously process transfers between four input/output devices and the main memory in a time-sharing manner by stealing cycles.

Each part within the DMA controller 20 operates as follows. In addition, each subchannel (26 ₀
26 ₃ ) and the corresponding ready flag registers (31 ₀ to 31 ₃ ) have the same operations, so unless it is particularly necessary, there is no need to distinguish between them.・Register 31" will be explained below as a representative example. Subchannel register 27 and its internal registers (28-
31), the input/output device (IO) 13, and the IO controller 14.

When the subchannel 26 selected by a priority circuit (not shown) that determines the priority of each subchannel is making a transfer response to the IO controller 14, the byte counter 29 becomes "0" and the mode・Register 3
If the chain flag is set to 1,
A chain request occurs.

When a chain request occurs, if the number of the subchannel 26 and the identification code ID of the VF ID register 25 match, and the valid flag VF is set, the chain is executed. As a result, chaining register 2
The contents of chain address register 22, chain-by counter 23, and chain mode register 24 in channel register 27 are stored in address register 28, byte counter 29, and mode register 31, respectively, in channel register 27. Copied.

When the chain processing is completed, the determination circuit 36 generates a chain end signal _C1 and outputs the VF ID.
The valid flag VF in the register 25 is reset, and the chain end flag CF is set in the chain status register 34.
When this chain end flag CF is set,
Subchannel 26 generates an interrupt request to CHP 16.

When a chain request occurs, if the number of the subchannel 26 does not match the identification code ID of the VF ID register, the determination circuit 36 generates an ID invalidation signal _C2 . This adds error information to update circuit 33 and sets error flag EF in status register 30 within subchannel register 27.

Furthermore, when a chaining request occurs, the number of the subchannel 26 matches the identification code ID, but if the valid flag VF has been reset, the control information has not yet been set in the chaining register 21. Therefore, the chain is put on hold. At this time, the determination circuit 36 generates a chain suspension signal _C3 and sets the chain suspension flag in the chain status register 34.
In addition to setting the PF, its subchannel 2
6 ready flag register 32 ready flag
Reset flag RF. Lady Flag RF
When the IO controller 14 resets, data transfer is not possible, so the DMA
Do not respond even if there is a request.

Byte count value of byte counter 29
When BC is “0” and there is no chain flag in the mode register 31, the determination circuit 36
is the transfer end signal (transfer stop)
_C4 is generated to notify the IO controller 14 of the completion of the transfer, and the main memory 11-IO controller 14
The data transfer between them is terminated. The transfer also ends when the error flag EF is set in the status register 30.

G ₂ (Description of Data Chain Operation) Next, the operations shown in FIGS. 1 and 2 will be explained with reference to the timing chart shown in FIG. 3.

FIG. 3 shows the timing diagram when data is transferred from the main memory 11 to the input/output device 13.
This shows the chart. Data is IO
After being stored once in a buffer (not shown) within the controller 14, it is sent to the input/output device 13. Therefore, main memory 11-IO controller 1
The transfer between the IO controller 14 and the input/output device 13 can be performed in advance by the number of buffer stages (on the contrary, the transfer between the input/output device 1
3 to the main memory 11, the data transfer between the IO controller 14 and the input/output device 13 can take precedence by the number of buffer stages).

In FIG. 3, a in the upper row shows the operation timing of the CHP 16, as in FIG.
The CHP 16 simultaneously processes processing 1, processing 2, and chain processing corresponding to the IO controller 14 in a time-sharing manner. Processing 1 has the highest priority, followed by chain processing and processing 2. b in the middle row shows the data transfer operation timing between the main memory 11 and the IO controller 14, and c in the lower row shows the data transfer operation timing between the IO controller 14 and the input/output device 13. Transfer between the main memory 11 and the IO controller 14 is performed between the IO controller 14 and the input/output device 13.
The transfer is performed in advance of the transfer by the number of buffer stages.

When the transfer 1 between the main memory 11 and the IO controller 14 ends at time _t1 , that is, when the byte counter 29 becomes "0", the chain flag of the MOBO register 31 is set and the chain operation continues. is indicated, subchannel 26 immediately issues a chain request. At this time, it is assumed that control information for the next transfer 2 is stored in the chaining register 21.

When the chaining register 21 receives this chain request, it confirms that the identification code ID in the VF ID register 25 matches the subchannel number and that its valid flag VF is set, and then performs chain processing. and set the chain address register 22,
The control information for transfer 2 stored in chain byte counter 23 and chain mode register 24 is copied to address register 28, byte counter 29 and mode register 31 in channel register 27, respectively.

Channel 26 performs transfer 2 following transfer 1, as shown in b, according to the control information for transfer 2.

On the other hand, when the chain processing is completed, the determination circuit 36 generates a chain end signal _C1 .
Valid flag VF of VF ID register 25
At the same time, the chain end flag CF is set in the chain status register 34. When this chain end flag CF is set, the subchannel 26 is connected to the CHP 16.
Generates an interrupt request for.

Since the CHP 16 is executing process 2, which has a lower priority than the chain process at time t ₁ , it immediately accepts the interrupt from the subchannel 26 and stores the control information for transfer 3 in the chaining register 21, as shown in a. At the same time, the valid flag VF of the VF ID register 25 is set.

When this chain processing is completed, CHP16
returns to process 2 again and executes that process.
Transfer 2 between main memory 11 and IO controller 14
At time t ₂ while processing is being executed, if there is an interrupt from process 1, which has the highest priority,
The CHP 16 interrupts process 2 and executes process 1.

When the transfer 2 between the main memory 11 and the IO controller 14 ends at time _t3 , a chain request is generated in the same manner as described above, and chain processing is executed. That is, the control information for transfer 3 in the chaining register 21 is copied to the subchannel register 27, and the control information for transfer 3 in the chaining register 21 is copied to the subchannel register 27, and
After the valid flag VF is reset and the chain end flag CF is set in the chain status register 34, an interrupt request is generated to the CHP 16.

However, at time _t3 , the CHP 16 is executing process 1, which has a higher priority than the chain process, so the interrupt request from the subchannel 26 is suspended, and the control information for transfer 4 is stored in the chaining register 25. will not be carried out. However, since control information for transfer 3 is stored in the subchannel register 27, between the main memory 11 and the IO controller 14,
As shown in b, after time _t3 , transfer 3 is performed following transfer 2.

When the transfer 3 between the main memory 11 and the IO controller 14 ends at time _t4 , a chain request is generated again. At this point, the value of the byte counter 29 is “0” (BC=0), and the VF ID
Although the valid flag VF of the register has been reset, its identification code ID matches the number of the subchannel 26, and the chain flag of the mode register 31 is set.

In this case, the determination circuit 36 generates the chain suspension signal _C3 , sets the chain suspension flag PF in the chain status register 34, and
Notify the CHP 16 that chain processing is on hold.

When the chain hold flag PF is set,
Since the chaining process is suspended, the contents of the chaining register 21 (actually nothing is stored therein) are not copied to the subchannel register 27, and the subchannel register 27 retains its previous state. In this case, the mode
Since the chain flag is set in the register 31, the determination circuit 36 does not notify the IO controller 14 of the completion of the transfer.

Conventionally, when chaining cannot be completed in time when transfer 3 is completed, the IO controller 14 is notified of the transfer completion as explained in FIG. 5, but in the present invention, the transfer completion notification is sent as described above. is not performed, and the request for transfer 4 (from the transfer between the IO controller 14 and the input/output device 13,
It only delays the response to requests (which have prior requests as shown in b and c).

Even if the transfer between the main memory 11 and the IO controller 14 is suspended, the IO controller 14 reads the data stored in the buffer, as shown in c.
Transfer 3 following transfer 2 between the input/output device 13 and
is going on.

When the process 1 ends at time _t5 , the CHP 16 resumes the suspended chain process. When the CHP 16 accepts an interrupt and resumes chain processing, the chain status
If the pending flag PF is set in the register 34, control information for transfer 4 following transfer 3 is stored directly in the subchannel register 27 instead of in the chaining register 21. At the same time, ready flag register 3
The ready flag RF, which had been reset in step 2, is set again. This allows subchannel 2
6 restores the data transfer between the main memory 11 and the IO controller 14 after time _t6 (transfer 4).
When transfer 5 follows transfer 4, CHP1
6 stores the control information for transfer 5 in the chaining register 21, and stores the control information for the transfer 5 in the VF/ID register 2.
Set the valid flag VF of 5. In response to these processes, the determination circuit 36 resets the chain end flag CF and suspension flag PF of the chain status register 34.

At this time t ₆ , the IO controller 14
As shown in c, transfer 3 is still being executed between the input/output device 13 and the input/output device 13.
Transfer 4 then takes place, with no interruption occurring in between.

Thereafter, at the end of transfer 4, transfer 5, . . . , the aforementioned chain request, chain processing, and interrupt request are generated, and the aforementioned processing is repeated according to each situation. Then, the value of the byte counter 29 becomes “0” (BC=0), and
When the chain flag in the mode register 31 becomes absent, that is, when all the predetermined series of data transfers are completed, the determination circuit 36
Generates transfer end signal _C4 and sends IO controller 1
4 of the end of the transfer, and terminates the data transfer between the main memory 11 and the IO controller 14.

In some cases, the transfer may end while the chaining register is being set and the chaining will be put on hold. In that case, the CHP 16 will
Valid flag VF of VF ID register 25
After setting , check the state of the pending flag PF in the chain status register 35 again. If the hold flag PF has been reset, the chain process ends as is, but if the hold flag PF has been set, the chain process during hold is restarted again.

Furthermore, although FIG. 3 shows an operation timing chart when a buffer is provided within the IO controller 14, the present invention is not limited to this embodiment; This also applies when a buffer is not provided. In that case,
When the transfer between the main memory 11 and the IO controller 14 is temporarily interrupted, the transfer between the IO controller 14 and the input/output device 13 is also temporarily interrupted, but the transfer process is not terminated and the interruption is recovered. , the transfer can be continued immediately without rebooting.

H [Effects of the Invention] As explained above, according to the data chaining method of the present invention, even if chaining registers cannot be set in time and chaining cannot be performed when the input/output operation being executed by the subchannel ends, Input/output operations can be continued without terminating and restarting input/output operations. Therefore, the number of times that the same input/output process is interrupted due to termination and the number of times that the same process is repeated are reduced, so that the performance of the system as a whole can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the configuration of the present invention, FIG. 2 is an explanatory diagram of an embodiment of the present invention, and FIG.
11 is an operational timing chart of the same embodiment, FIG. 4 is an explanatory diagram of the conventional data chain system, and FIG. 5 is an operational timing chart of FIG. 4. is the main memory, 12 is the central processing unit, 13 is the input/output device (IO), 14 is the input/output device controller (IO controller), 15 is the channel mechanism, 16
is channel processor (CHP), 20 is DMA
controller, 21 is a chaining register;
25 is a valid flag/identification code register (VF/ID register), 26 is a subchannel, 27
3 shows a subchannel register, 32 a ready flag register, and 36 a determination circuit, respectively.

Claims (1)

[Claims] 1 Main memory 11, input/output sections 13 and 14, channel processor 16, and DMA controller 2
0, the DMA controller 20 includes a subchannel 26 for controlling the input/output operation being executed, and a chaining register 21 in which control information for controlling the next input/output operation is set. The control information is copied from the chaining register 21 to the subchannel register 27 provided in the subchannel 26, and the input/output unit 13,
14 and multiple areas in the main memory 11, (a) Corresponding to the subchannel 26, it is determined whether the subchannel 26 is operable or not. register 32 indicating
(b) a register 25 indicating whether the control information of the chaining register 21 can be used; (c) a subchannel 26 if the control information of the chaining register 21 is unavailable when data chaining is to be performed; a determination circuit 36 that displays in the register 32 that the DMA transfer request is inoperable and suspends responses to future DMA transfer requests, and notifies the channel processor 16 that chain processing is suspended; (d) When the channel processor 16 restarts chain processing, the channel processor 16 registers the subchannel register 27.
(e) The subchannel 26 restarts DMA transfer when the register 32 indicates that the subchannel 26 is operable. A data chain method in DMA transfer characterized by: