JPS6329868A - Dma controller - Google Patents

Abstract

PURPOSE:To continuously execute DMA transfer to plural memory blocks as a series of operation by setting up information for data transfer in a 2nd register during the execution of DMA transfer based upon the contents of a 1st register. CONSTITUTION:A microprocessor sets up the information of a memory block to which data are to be transferred in the 1st memory address register 1 and a 1st transfer frequency register 2 and sets up a DMA request permission flag 6 to make the memory block DMA transfer enabling state. At the time of input of a DMA request signal 7, a timing control circuit 5 is driven, DMA transfer is started and a memory address 11 and a control signal 12 are outputted to an external. At the time of starting the DMA transfer, a write permission flag 8 is set up and writing in a 2nd memory address register 3 and a 2nd transfer frequency register 4 is permitted. Consequently, the DMA transfer can be continuously executed during the input of the DMA request signal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to direct memory access (DMA) controllers, particularly those arranged in discontinuous areas. ! The present invention relates to a DMA controller having a function of performing DMA transfer to multiple memory processors.

[Conventional technology]

In the conventional DMA controller of this building, DMA transfers to a plurality of memory processors arranged in discontinuous areas could be executed according to the following procedure.

(1) Information on the memory block to be transferred (memory address and number of transfers) is set in the microprocessor, which is the DMA controller, to enable the DMA controller to operate.

+2) The DMA controller executes DMA transfer, and when the transfer is completed, sends an interrupt request to the microprocessor and stops operation.

(3) By microprocessor woko and interrupt processing, DM
The next memory processing information is set in the A controller, and the DMA controller is made executable again.

[Problem that the invention seeks to solve]

The conventional DMA controller described above is used when executing DMA transfers to multiple memory processors located in discontinuous areas, and when the DMA transfer to the memory processors targeted for data transfer is completed. Because it was necessary to set the information for the next nine programs in memory, DMA transfer could not be performed while that information was being set, and as a result, the DMA
[Flat film for solving the problem] The DMA controller of the present invention has a first register that holds information set for data transfer, and a first register that holds information set for data transfer; and a second register that holds the information set for the transfer.

Data transfer based on the contents of the first register is possible only when the DMA request ffc''r flag is set when the above information is set in the first register, and the DMA request permission flag is set. A write permission flag that is set when the program starts and is reset when the above information is set in the second register, which can only be accessed in this set state, is provided, and data transfer based on the contents of the first register is provided. When the data transfer is completed, the contents of the second register are transferred to the first register depending on the state of the write permission flag, the DMA request permission flag is reset, and the completion of data transfer is reported to the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a diagram of an embodiment of the present invention.

In FIG. 1, the first memory address - register 1
and the first transfer count register 2 have information regarding the currently executing DMA transfer, and the up/cuff/first transfer count register 2 has information regarding the DMA transfer currently being executed.
It operates as a Dow 7 counter. Second memory
It has information regarding the DMA transfer to be executed subsequently after the completion of the DMA transfer by the address register.

The timing control circuit 5 controls the internal timing of the DMA controller, and the DMA5 request permission flag 6 is a flag that controls whether to enable or disable the DMA request signal 7, and is a microgross flag.

It is set or reset by a command from the original or by the internal state of the DMA controller.

The write permission flag 8 is a flag indicating that information has been written to the second memory address register 3 and the second transfer count register 4.
Set or reset depending on the write operation to register 3 and second transfer count register 4 or the internal state of the DMA controller.

This flag can also be read by the microprocessor.
This circuit generates an interrupt request signal 10 to notify the microprocessor of the completion of A transfer.

Next, the operation of this embodiment will be explained.

(1) The microprocessor sets information on the memory processor to be data transferred in the first memory address register 1 and the first transfer count register 2, and
The A request permission flag 6 is set to a state in which DMA transfer can be executed.

(2) When the DMA request signal 7 is input, the timing control circuit 5 operates, DMA transfer is started, and the memory address 11 and 1WIJ # signal 12 are output to the outside. Each time one DMA transfer is executed, the first memory address register 1 and the first transfer count register 2 are incremented by +1 and -1, respectively. Also, when a DMA transfer is started, write permission 7 lag is added. 8 is set, and writing to the second memory address register 3 and second transfer count register 4 is permitted.

(The 31D MA transfer is executed continuously while the DMA request signal 7 is being input, and during this time the microprocessor,
The next memory program information can be set in the second memory address register 3 and the second transfer count register 4 by monitoring the write permission flag 8. When the information is set, the write permission flag 8 is reset.

(4) Boundary Although the DMA transfer being executed ends when the contents of the first transfer count register 2 become 0, the subsequent operation differs depending on the state of the write permission flag 80 at that time.

(4,1) When write permission 7 and 8 are reset. In this case, the information of the next memory block is set in the second memory address register 3 and the second transfer count register 4. , and executes the DMA transfer to the next memory processor. That is, when the transfer end signal 13 is generated, the load signal 14 is sent to the first memory e-address register 1 and the first transfer count register 2, and the second memory address register 3 is sent to each of them.
and the contents of the second transfer count register 4 are set.

Additionally, since the DMA hit permission flag 6 is set, when the DMA request signal 7 is inputted, DMA transfer to the next memory block is automatically executed. Further, in this case, the interrupt request signal 0 is not generated.

(4, 2) When the write permission flag 8 is set In this case, the information for the next Memory Fist Pro is set in the second memory address register 3 and the second transfer count register 4. Since there is no DMA transfer, the DMA transfer ends. That is, when the farewell completion signal [3] is generated, a stop signal 15 is sent to the DMAe request permission flag 6, the DMA approval request permission flag 6 is reset, and the DMA1 request signal 7 is no longer accepted. F) DMA@j'F- is stopped.

Further, the stop signal ]4 is also sent to the interrupt generation circuit 9, and an interrupt request signal 10 is generated to notify the microprocessor of the end of the transfer.

〔Effect of the invention〕

As explained above, the DMA controller of the present invention sets information for data transfer in the second register while executing DMA transfer based on the contents of the first register.
After the DMA transfer based on the contents of the second register is completed, the DMA transfer based on the contents of the second register is subsequently executed, so DMA1 transfer is executed to multiple memory blocks located in discontinuous areas. In case, D
There is no need to inhibit DMA transfer to set information to the MA controller, and DMA transfer to multiple memory processors can be executed continuously as a series of operations.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing one implementation of the present invention. 1...First memory address register, 2
...First transfer count register, 3...
Second memory address register, 4... Second transfer count register, 5... Timing control circuit, 6... DMA request permission flag, 7...
・DMA request signal, 8...Write permission flag, 9...Interrupt generation circuit, ]O...
Interrupt request signal, 11... Memory address, 12... Control signal, 13... Transfer end signal, 14... Load signal, 15...・・・・・・
- Stop signal, 16...Register update signal.

Claims (1)

[Claims] A first register that holds information set for data transfer, and a second register that holds information set for the next data transfer.
a DMA request permission flag that is set when the information is set in the first register; and data based on the contents of the first register that is possible only when the DMA request permission flag is set. and a write permission flag that is set when the transfer starts and is reset when the information is set in the second register, which is possible only in the set state, and data based on the contents of the first register. When the transfer is completed, depending on the state of the write permission flag,
A DMA controller, characterized in that the content of the second register is transferred to the first register, the DMA request permission flag is reset, and the completion of data transfer is reported to the outside.