JPH04260955A - Microcomputer - Google Patents

Abstract

PURPOSE:To shorten a period from the end of a transfer execution state up to its start and to attain rapid operation by providing a DMA controller with two storage means for storing current DMA transfer information and succeeding DMA transfer information. CONSTITUTION:A microcomputer 100 is constituted of a CPU 10, the DMA controller 20 to be a peripheral unit, an interruption controller 30, a serial data receiving unit 40, and the other peripheral unit 50. The DMA controller 20 includes a current register block 202 for storing information necessary for current DMA transfer, a next register block 203 for storing information necessary for DMA transfer to be executed next and a save register block 204 for storing the transfer frequency information of the block 202 and control/state information. Consequently the switching of DMA transfer can rapidly be executed and a transfer inhibiting period can be shortened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to microcomputers, and more particularly to microcomputers incorporating a direct memory access (DMA) controller.

0002

[Background Art] Modern microcomputers, which are required to have higher functionality and higher speeds, have interrupt controllers, timers, etc.
It incorporates various peripheral units such as counters and serial data communication devices. Data transfer is required between such peripheral units and memory, but if such data transfer is performed by a central processing unit (CPU) with the intervention of software (program), data processing efficiency decreases. Therefore, data transfer between peripheral units and memory is
It is common to have the DMA controller execute this instead of the PU.

The DMA controller includes an address register that stores address information of the memory to be accessed, a terminal counter register that stores the number of data to be transferred, and a control register that stores control data such as the data transfer direction and memory address update direction. It has registers, and necessary information is initially set in these registers by the CPU. When the peripheral unit requests data transfer from the DMA controller, the DMA controller obtains the right to use the bus from the CPU and executes the data transfer between the peripheral unit and memory. When the data transfer is completed, the DMA controller hands over the right to use the bus to the CPU and enters a waiting state for the next data transfer request. When the number of data thus transferred reaches the number of data set in the terminal counter register, the DMA controller issues an interrupt request to the CPU. Based on the request, the CPU executes the interrupt processing routine, resets the necessary information in the above register, and
Enables the next data transfer.

0004

[Problem to be Solved by the Invention] The DMA controller is in a data transfer prohibited state during the period from the time when it issues an interrupt request to the CPU until the time when the information necessary for the next data transfer is reset. A peripheral unit may issue a data transfer request during this prohibited period. Such requests will not be accepted and will be put on hold. The length of the data transfer prohibition period depends on the priority of interrupt requests from the DMA controller and the number of transfer channels supported by the controller, but if the data transfer prohibition period is long, the peripheral circuit where the data transfer request is pending may be in a state where it issues a data transfer request again during the suspension period. For example, a serial data receiving device issues a data transfer request every time it receives a predetermined number of bits of data, but if the reception of the next data is completed before the previous data is transferred to memory, the previous data is destroyed. Eventually, a reception overrun error occurs. As another example, in a serial data receiving device, data to be transmitted next is not transferred and a transmission underrun error occurs. Reception overrun errors and transmission underrun errors are more likely to occur as serial lines become faster. Even if you increase the number of receive/transmit data buffer stages, errors will still occur if data transfer is suspended for more than that number of stages, and if you increase the number of buffer stages sufficiently to match the high-speed serial line, the hardware will increase. bring.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a microcomputer with a DMA controller that substantially eliminates the period from the end of the current data transfer execution state to the start of the next data transfer execution state.

Another object of the present invention is to provide a microcomputer with a built-in DMA controller that can prevent errors from occurring due to pending data transfer requests from peripheral units.

Still another object of the present invention is to provide a microcomputer with a built-in DMA controller that can support a serial data communication device for high-speed serial lines.

[0008]

[Means for Solving the Problems] A microcomputer according to the present invention includes a CPU and a DMA controller that executes data transfer between the peripheral unit and memory based on a data transfer request from the peripheral unit, and the DMA controller includes: a first storage means for storing first information necessary to execute the current DMA transfer;
The second DMA transfer necessary for the next DMA transfer that should be started after the transfer is completed.
a second storage means for storing information on the data; an execution means for executing data transfer based on the data transfer request using the first information; and means for enabling the execution means to execute data transfer using the second information and issuing an interrupt request to the CPU when the desired number of data is reached, the execution means It is characterized in that data transfer is executed using the second information based on subsequent data transfer requests from peripheral units.

With this configuration, when the number of transferred data reaches the determined number and the current DMA transfer ends, the execution means becomes ready to execute the DMA transfer based on the second information. Therefore, data transfer between the peripheral unit and memory can be executed in response to data transfer requests that are successively issued from the peripheral unit without waiting for the CPU to reset the information necessary for DMA transfer.

On the other hand, the CPU interrupts program execution based on an interrupt request generated by the end of the current DMA transfer, and obtains third information necessary for the next DMA transfer to be activated after the completion of the next DMA transfer. is supplied to the DMA controller. This third information is stored in the second storage means when the second information is copied from the second storage means to the first storage means, and is stored between the execution means and the second storage means. When exchanging information, the information is stored in the first storage means.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a microcomputer system constructed using a microcomputer 100 according to a first embodiment of the present invention. This microcomputer 100 includes a CPU 10, a DMA controller (DMAC) 20 as peripheral units, an interrupt controller (INTC) 30, and a serial data receiving unit 4.
0 and other units 50 such as timers and counters. These are configured on the same semiconductor substrate, and the internal bus 6
0 and interconnected.

The CPU 10 fetches and executes instructions from a program memory 110 connected via a system bus 130 to process operand data. Data memory 120 is also connected to system bus 130 .

The INTC 30 receives a plurality of interrupt request signals including the interrupt request signals 23 and 51 from the DMAC 20 and the peripheral unit 50, and when two or more interrupt requests occur simultaneously, one of them is selected according to a predetermined priority order. , and generates an interrupt processing request signal 31 and supplies an interrupt vector number 32 to the CPU 10. Based on this interrupt processing request, the CPU 10
temporarily interrupts the program processing being executed, saves the program counter, program status word, and general-purpose registers (all not shown), and executes the interrupt processing routine.

Serial data receiving unit 40 receives serial data supplied from the outside via serial line 150. Serial data is in shift register 40
5 in order. When a predetermined number of bits (for example, 8 bits) of data is received, the data is transferred to the buffer register 404, and the shift register 405 starts receiving the next serial data. When the data is transferred to the buffer register 404, the reception control unit 401 activates the DMA transfer request signal 42 and requests the DMA 20 to transfer the data. The data transferred to the buffer register 404 reaches EO indicating the end of one frame of serial data transfer.
For F (End Of Flame) code,
The block switching signal 41 is activated and the DMAC 20
request block switching. The fact that the EOF code has been received or that an error has occurred in the received data is recorded in the status register 402. The reception control unit 401 uses DMA
The contents of buffer register 404 are output to internal bus 60 in synchronization with data output instruction signal 25 from C20. In addition, the status save instruction signal 24 from the DMAC 20
In response to this, the contents of the status register 402 are saved in the status save register 403.

[0016] The DMAC 20 has a transfer control unit 201,
The control unit 201 executes DMA data transfer between the unit 40 and the memory 120 based on the control information stored in the current register block 202. The control information stored in register block 202 includes transfer count information indicating the number of data transfers, memory address information indicating the access address of memory 120, and control/status information. The control/status information includes the direction of DMA data transfer (i.e., from memory to peripheral unit or from peripheral unit to memory, in this example from serial receiving unit 40 to memory 120), memory address update direction, and DMA transfer request. It has transfer request acceptance permission information indicating whether or not to accept the DMA.
Contains block continuation instruction information indicating whether or not transfer can be continued to the next block. DMAC 20 further includes a next register block 20 according to the present invention.
3 and a save register block 204. The next register block 203 stores information necessary for the next DMA transfer to be executed after the current DMA transfer ends, that is, transfer count information, memory address information, and control/status information for the next DMA transfer. The save register block 204 saves the transfer number information and control/state information of the current register block 202. The transfer control unit 201 issues a hold request (HLD) to the CPU 10.
RQ) signal 21 and receives a hold acknowledge (HLDACK) signal 22 from the CPU 10, the bus 60,1
30 and executes data transfer from the serial receiving unit 40 to the memory 120. Each time data transfer is executed, the number of transfers of the current register block 202 is 1.
At the same time, the memory address 202 is updated. When the number of transfers becomes 0, that is, when the number of transferred data reaches the number of data specified by the current DMA transfer, or when the block switching request signal 41 based on reception of the FOF code from the unit 40 becomes active, the current register block 202 Transfer count information and control/state information are saved in the save register block 204. Then, when the block continuation instruction information included in the saved control/state information instructs "continuation", the contents of the next register block 203 are copied to the current register block 202, and an interrupt request signal 23 is generated. . When the block continuation instruction information indicates "non-continuation", the interrupt request signal 23 is generated without copying from the next register block 203 to the current register block 232.

Data memory 120 stores operand data to be and have been processed by CPU 10, but also stores operand data to be processed by CPU 10, and also stores operand data to be processed by CPU 10.
It has N blocks 122, 124, . . . , 126 to which data received by is to be transferred. Block control data area 123 corresponds to each of these blocks.
, 125, . . . , 127 are provided. Each of the block control data areas includes a transfer count data area indicating the size of the corresponding block, a memory address data area indicating the start address of the corresponding block, and control/state of DMA transfer between the corresponding block and the receiving unit 40. It has a data area, a peripheral status save data area to which the contents of the status save register 403 of the receiving unit 40 are to be transferred, and a next address data area that stores the start address of the control data area for other blocks. The data memory 120 further has a storage area 121 for storing control data area addresses.

The specific operation of this microcomputer will be described below in detail with reference to the operation flows shown in FIGS. 2 and 3.

The CPU performs initial settings before starting the DMAC 20. That is, the first to Nth blocks 122
, 124,..., 126 are assigned to the data memory 120●
, corresponding block control data areas 123, 125,
... 127, the data is written as described above. Note that the block continuation instruction information in the DMA control/status data of the first to (N-1) block control data areas instructs "continuation", and that of the Nth block control data area instructs "non-continuation". Suppose there is. Further, the next address data of the first block control data area contains the start address of the second block control data area, that of the second block control data area contains the start address of the third block control data area, and the (N-th) 1) It is assumed that the start address of the Nth block control data area is set in that of the block control data area. The control data area address 121 is set to the starting address of the first block control data area 123. The CPU 40 also sets information necessary for serial data reception, such as the speed of the serial line 150, in the serial data reception unit 40, and permits serial reception. Then, the transfer count data, memory address data, and DMA control/status data of the second block control data area 125 are set in the next register block 203 of the DMAC 20, and the first
The transfer count data, memory address data, and DMA control/status data in the block control data area 123 are set, and the DMAC 20 is activated. CPU 10 continues to fetch and execute instructions from program memory 10.

On the other hand, the activated DMAC 20 operates according to the operation flow shown in FIG. That is, it is checked whether the block switching request signal 41 accompanying the reception of the EOF code from the serial data receiving unit 40 is active (251), and it is checked whether the data transfer request signal 42 is active (252).

The serial data receiving unit 40 has also been activated and is receiving serial data transmitted via the serial line 150. When data of a predetermined number of bits is received, it is checked whether the data is an EOF code or normal data, and a signal 41 or 42 is generated.

Assuming that the serial data receiving unit 40 generates the data transfer request signal 42, the transfer control unit 20
1 activates the HLDRQ signal 21 and connects the bus 60;
130 is requested from the CPU 10 (253). C
The PU 10 temporarily suspends the program processing being executed, puts the internal device in a hold state, and sends the HLDACK signal 22 to the DMAC 2.
Return to 0. The transfer control unit 201 has an active level of HL.
When the DACK signal 22 is detected (254), the memory address of the current register block 202 is transferred to the bus 60, 1.
30 to the data memory 120 and generates a data output instruction signal 25 to cause the serial data receiving unit 40 to output the received data to the bus 60. Thus, the received data is stored in the first block 1 in the memory 120.
It is transferred to the first address of No. 22 (255). After transfer,
The HLDRQ signal 21 is withdrawn and the right to use the bus is returned to the CPU 10. The transfer control unit 201 is the current register block 2
The memory address of 02 is updated and written back, one is subtracted from the transfer count data and written back (257). The updated address may be used as the access address for the first block 122, if desired. The transfer control unit 201 determines whether the subtracted number of transfers is zero (258), and returns to step 251 if it is not zero. Such processing is executed every time the data transfer request signal 42 becomes active.

When the block switching request signal 41 is generated or the number of transfers becomes zero, that is, when the first block 122
When is filled with received data, processing moves to step 259. That is, the transfer number information and control/state information of the current register block 202 are saved in the save register block 204. The transfer control unit 201 determines block continuation instruction information in the saved control/state information (260). In this explanation, since the same information instructs "continue", the process moves to step 261, and the contents of the next register block 203 are changed to the current register block 20.
Copied to 2. Thus, the DMAC20
A state is reached in which DMA transfer between the serial data receiving unit 40 and the second block 124 of the memory 120 can be performed without waiting for resetting by the serial data receiving unit 10. Transfer control unit 201
Thereafter, it generates a peripheral save signal 24 and an interrupt request signal 23, and proceeds to step 251. Therefore, after this, when the serial data receiving unit 40 generates the data transfer request signal 42, the received data is transferred to the second block 12.
It will be transferred to 4.

On the other hand, in response to the peripheral save signal 24, the reception control section 401 saves the contents of the status register 402 in the status save register 403.

The INTC 30 generates an interrupt processing request to the CPU 10 in response to the interrupt request signal 23 from the DMAC 20. Based on the request, the CPU 10 interrupts program execution, saves information necessary for resuming the interrupted program execution to the stack area (not shown) of the data memory 120, and executes the interrupt processing routine of FIG. 3.

In this interrupt processing routine, the CPU
10 first reads the saved status information from the status save register 132 in the receiving unit 40 (
301), and checks whether an error has occurred in the received data or reception status (302). If an error has occurred, as error processing 303, the operation of the DMAC 20 and the data receiving unit 40 is stopped, the serial data transmission source is requested to retransmit the data, and the DMA
C20 and unit 40 are reset. If no error occurs, the contents of the status save register 403 are transferred to the peripheral status save data area of the first block control data area 123, and the contents of the save register block 204 of the DMA 20 are transferred to the transfer count data area of the same area 123 and the DMA control data area. /Transfer to status data area (
304). For this process, the start address of the data area 123 is stored as the control data area address 121, and the address of each data area is calculated from the same address and a predetermined offset amount for each data area in each block. be done. Of course, DMAC20
The addresses of each register in the receiving unit 40 are determined in advance. Then, the next address data of the first block control data area 123, that is, the start address of the second block control data area is set as the control data area address 121. Next, the block continuation instruction information of the DMA control/state data saved in the first block control data area 123 is determined (30
5). In this explanation, since the information instructs "continuation", the newly set control data area address 121 and the next address data in the second block control data area 125 are used to create the third block control data Transfer count data, memory address data, and DMA control/status data in an area (not shown) are transferred to the next register block 203 of the DMAC 20 (306).

Returning to FIG. 2, when the block continuation instruction information instructs "non-continuation" in step 260, the transfer control unit 201 transmits the signal without copying the contents of the next register block 203 to the current register 202. 2
4 and 23, the DMAC 20 enters a waiting state for data resetting in the CPU 10, and enters a DMA transfer prohibited state. Therefore, in the CPU interrupt processing routine shown in FIG. 3, the process moves to step 307 after step 305, and the transfer count data, memory address data, and DMA control/status data in the second and third block control data areas are set to the current state. are transferred to the register block 202 and next register block 203, respectively, and the DMAC
20 is restarted.

After executing step 306 or 307, the CP
U10 performs processing on the data transferred to the first block 122 (308). After execution, data memory 1
The information saved from 20 is restored and the interrupted program is restarted.

Since the information on the number of transfers of the save register block 204 is also transferred to each block control data area, even if the above-mentioned block switching is executed in response to the block switching request signal 41 upon reception of the FOE code, the number of transfers for each block is also transferred. It can be determined whether data is being transferred.

[0030] In this way, if the block continuation instruction information is set to "continue", even if a predetermined number of data is transferred or a FOE code is received, the DMAC 20 will be in the data transfer permission state to the next block. Therefore, it is possible to prevent reception overrun errors from occurring.

When the present microcomputer 100 also incorporates a serial data transmitting unit, a current register block, a next register block, and a save register block for this unit are further prepared in the DMAC 20, and a serial data transmitting unit and a receiving unit are also provided. By performing data transfer in a time-division manner, both reception overrun errors and transmission underrun errors can be prevented.

Referring to FIG. 4, the microcomputer 101 according to the second embodiment of the present invention has a DMA interface between the serial data receiving unit 40 and the local memory 400.
It has a DMAC 20 that performs transfer. Note that the same components as those in FIG. 1 are indicated by the same numbers and the description thereof will be omitted. DMAC
20, receiving unit 40 and local memory 400 are interconnected by a local bus 450. When the receiving unit 40 issues a data transfer request, the transfer control unit 20
1 obtains the right to use the local bus from a processor (not shown) that manages the local bus 450 using the HLDRQ signal 21 and the HLDACK signal 22, and transfers data from the receiving unit 40 to the local memory 400.

In such a configuration, the CPU 10 shown in FIG.
Since the interrupt processing routine is not temporarily interrupted by DMA transfer, the processing efficiency of the CPU can be further improved. The local memory 400 is also under the control of the microcomputer 101, and the local bus 450 is
If used as a dedicated bus for A transfer, the transfer control unit 201 can perform DMA transfer without using the signals 21 and 22.

The interrupt processing routine shown in FIG. 3 is stored in the program memory 110 and can be changed relatively freely by the user. For example, error checking (302
) and data processing (308) in all blocks 12
2, 124, . . . , 126 may be executed all at once after the data transfer to 2, 124, . However, steps 304 to 306
It is preferable to execute this as long as it instructs block continuation.

By the way, in executing the interrupt processing routine shown in FIG. 3, the CPU 10 first checks the current state of the interrupted program execution, that is, the contents of the program counter (PC), program status word (PSW), and general-purpose registers. This involves the so-called overhead of saving the data in the data memory 120 and restoring the saved content after executing the interrupt processing routine to restart the program. Eliminating this overhead and using DMA
If the microcomputer itself executes the rated processing based on the interrupt request from the C20 as if it were part of the hardware, processing efficiency can be further increased and the burden on the user's program can be reduced.

A configuration for this purpose is shown in FIG. 5 as a third embodiment. In addition, in this embodiment, only the CPU 15 and INTC 30 of the microcomputer are shown in FIG.
The other configurations are the same as those in FIG. 1, so they are omitted. The present CPU 15 employs a microprogram control method, and each instruction stored in the program memory 110 executes a corresponding series of microinstructions (ie, a microprogram) to achieve this function. Since the microprogram is invisible to the user, it is completely part of the hardware for the user.

That is, program counter (PC) 1
The contents of 51 are transferred to buses 60, 130 via address bus driver 153, whereby the instructions read from program memory 110 are transferred to data buffer 154.
It is temporarily stored in the instruction register (IR) 155 via the instruction register (IR) 155. Instructions from the IR 155 are decoded by a decoder 156 and supplied to an execution unit 158. The execution unit has a microprogram memory 1585, and a series of microinstructions is read and executed by setting the microaddress of the decoded instruction in the microprogram pointer 1584. The execution unit 158 further includes an arithmetic logic unit (ALU) 1581 and a program status word (PSW) 1582 that temporarily stores the operation status thereof.
, has a temporary register 1583, and has a general-purpose register 1
The functions of the instructions stored in the IR 155 are performed by executing a series of microinstructions in cooperation with the IR 157. A control signal group 159 output from the execution unit 158 is a sequence control signal for executing instructions.

The microprogram memory 1585 stores the macro service microprogram 15 according to this embodiment.
86 are stored. Macro services will be explained in detail later. This macro service program 1586 is activated when an interrupt request from INTC 30 specifies a macro service request.

[0039] That is, INTC30 is DMAC20
Flag 3 that specifies whether to process the interrupt request from as a macro service or a normal vector interrupt.
It has 3. When flag 33 is set, macro service is designated, and when cleared, vectored interrupt is designated. When INTC 30 receives an interrupt request, it generates interrupt processing request signal 31 to execution unit 158 and stores interrupt mode information 32-1 in IR 155. Furthermore, the vector number information 32-2 is sent to the execution unit 15.
Supply to 8. As a result of decoding the interrupt mode information 32-1, if a vectored interrupt is specified, the start address of the interrupt processing routine is obtained from the vector number information 32-2, and the PC
151, PSW 1582, and the contents of the general-purpose register 157 are saved in the data memory 120, the above-mentioned start address is set in the PC, and the interrupt processing routine is executed. On the other hand, when the interrupt mode information 32-1 specifies macro service, the start micro address of the macro service micro program 1582 is obtained from the vector number 32-2, this is set in the pointer 1584, and the micro program is executed. . At this time, the contents of the PC 151, PSW 1582, and general-purpose register 157 are not saved and remain as they are, and updating of these contents is prohibited.

Next, the operation will be explained in detail. The CPU 15 executes the program stored in the program memory 110 as described in FIG.
0, serial data receiving unit 40 and DMAC2
Perform initialization to 0. However, in this embodiment, DM
A Following the macro service as control/state information, C
It also includes vector interrupt request designation information that causes the PU 15 to transition to vector interrupt processing. In this explanation, vector interrupt requests are not specified in the first to (N-1) blocks;
It is specified in the Nth block. In addition, the first to (N
-1) In the block, the block continuation designation information is "continuation", and in the Nth block, it is "non-continuation". Furthermore, in this embodiment, the flag 33 of the INTC 30 is set at the time of the initial setting. After such initial settings, the CPU
15 continues to fetch instructions from the program memory 110 and execute them.

On the other hand, the DMAC 20 operates according to the flow shown in FIG. 2, and each time data of a predetermined number of bits is received, the data is transferred by DMA from the receiving unit 40 to the first block 122 of the data memory 120. . Then, in this explanation, when the transfer count data of the current register block 202 becomes zero or the FOF code is received, the transfer count data and control/state data of the current register 202 are saved in the save register block 204, and the next The contents of register block 203 are copied to current register block 202 (see 2 in the figure).
59 to 261), then the peripheral save instruction signal 24 is generated and the interrupt request signal 23 is generated.

Since flag 33 is set, IN
The TC 30 transfers the macro service mode designation information 32-1 to the IR 155 in response to the interrupt request signal 23. Thus, the macro service microprogram is
1. Startup is performed with the contents of the PSW 1582 and general-purpose register 157 left as they are without being saved. A flowchart of this macro service microprogram is shown in FIG. That is, the contents of the status save register 403 and the contents of the save register block 204 of the DMAC 20 are transferred to the corresponding areas of the first block control data area 123 using the value of the control data area address 121 of the data memory 120 (
601). Block continuation instruction information in the saved DMA control/state data is checked (602). In this explanation, since the instruction is "Continue", the next address data of the first block control data area 123 is set as the area address 121 (603), and the next address data 2 of the same address and the second block control data area 125 is set as the area address 121 (603). Using this, the transfer count data, memory address data, and DMA control/status data in the third block control data area are transferred to the next register block 203 of the DMAC 20 (604). After this, D transferred to the first block control data area 123
Vector interrupt request instruction information in the MA control/state data is checked (605). In this explanation, since no vector interrupt request is made, the macro service is ended.

[0043] When the macro service ends, the PC 151
, PSW 1582, and general-purpose register 157 are permitted to be updated, and execution of the interrupted program is resumed. CPU processing efficiency is further increased because there is no overbed caused by program interruption and restart.

If "non-continuation" is specified in step 602, the process moves to step 605. If a vector interrupt request is specified in this step, the flag 33 is cleared (606) and the macro service is ended.

By clearing the flag 33, I
NTC 30 sets vector interrupt mode code 32-1 to IR/55 again, which causes the user program interrupt routine to be activated.

Various processes can be considered for the processing by this interrupt routine depending on the block continuation instruction information and/or vector interrupt request instruction information corresponding to each block. In this explanation, a vectored interrupt is activated after data is transferred to the Nth block 126, so the interrupt processing routine executes error checking based on the peripheral state save data in each block and processing for each data at once. be done.

As described above, according to this embodiment, the DMAC
Since the necessary data transfer between 20 and the data memory 120 is executed as part of the microcomputer hardware as a macro service by a microprogram, the execution efficiency of data processing is further increased and the burden of program creation is reduced to the user. It can be reduced.

In this embodiment as well, the DMA is performed according to FIG.
C20 may perform DMA transfers between receiving unit 40 and local memory 400.

[0049]

[Effects of the Invention] As described above, according to the present invention, the DMA
Switching of transfer blocks can be performed at a very high speed of several clocks, and the transfer inhibition period can be extremely shortened.
It is also possible to deal with cases where the A transfer request issuance period is short.

It is clear that the present invention is not limited to the above embodiments and can be modified as appropriate. For example, instead of copying the next register block 203 to the current register block 202, a register to be referenced by the transfer control unit 201 is copied to the next register block 202 using a multiplexer.
It may be switched to 03. At this time, the next information is loaded into register block 202, which becomes the next register block.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram using a microcomputer according to a first embodiment of the present invention.

FIG. 2 is an operation flowchart of the DMAC shown in FIG. 1;

FIG. 3 is a flowchart showing an example of an interrupt processing routine of the microcomputer shown in FIG. 1;

FIG. 4 is a system block diagram according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a CPU of a microcomputer according to a third embodiment of the present invention.

FIG. 6 is a flowchart of a macro service microprogram of the CPU shown in FIG. 5;

Claims (7)

[Claims] 1. A DMA controller that executes data transfer between the peripheral unit and memory in response to a data transfer request from a CPU and a peripheral unit, wherein the DMA controller is configured to perform data transfer between the peripheral unit and memory, and the DMA controller is configured to perform data transfer between the peripheral unit and memory in response to a data transfer request from a CPU and a peripheral unit. a first storage means for storing first information, a second storage means for storing second information necessary for the next DMA transfer to be activated after the completion of the current DMA transfer; an execution means for executing data transfer in response to the data transfer request using the information; and an execution means for executing the data transfer in response to the completion state of the DMA transfer using the first information; and means for issuing an interrupt request to the CPU, and the executing means executes the data transfer using the second information in response to the subsequent data transfer request. A microcomputer characterized by executing. 2. The CPU includes means for setting, in the DMA controller, third information necessary for a further next DMA transfer to be activated after the completion of the next DMA transfer in response to the interrupt request; 2. The execution means of the DMA controller, when the DMA transfer using the second information is completed, uses the third information to execute subsequent data transfer in response to the data transfer request. 1. The microcomputer according to 1. 3. The CPU further comprises a program counter for specifying an address of an instruction to be executed and a program status word for storing an instruction execution status, and the means of the CPU is configured to read the third information from the DMA. 3. The microcomputer according to claim 2, wherein settings are made to the controller while the contents of the program counter and the program status word are maintained as they are without being saved. 4. A DM that executes data transfer between the CPU and peripheral units and memory in response to a data transfer request.
A controller, the DMA controller includes an execution means for performing the data transfer, a first storage means for storing information necessary for the execution means to perform the data transfer, and a first storage means for storing information necessary for the execution means to perform the data transfer, and a first storage means for storing information necessary for the execution means to perform the data transfer, and a second storage means for storing necessary information; and a second storage means for storing necessary information; D using the information copied to the storage means of and copied to the execution means.
1. A microcomputer comprising: means for enabling MA transfer. 5. When the store information in the second storage means is copied to the first storage means, the CPU further stores information necessary for the next DMA transfer to be activated into the second storage means. 5. The microcomputer according to claim 4, further comprising means for storing. [Claim 6] Direct memory access (hereinafter referred to as D
A state saving storage means that issues a transfer request signal (denoted as MA), issues a DMA transfer end instruction signal when processing is completed, and saves and stores the internal state when the processing is completed or when a state saving instruction signal is detected. a peripheral circuit, first, second, and third types of DMA control storage means including at least a DMA control information storage section including DMA transfer continuation instruction information and a DMA transfer number storage section; and a DMA transfer request signal. When detected, a DMA transfer is performed between the peripheral circuit and the memory, and the value of the DMA transfer number storage section in the second DMA control storage means is updated, and if the update results in a predetermined value or the DMA If either a transfer end instruction signal is detected and the DMA transfer continuation instruction information in the second DMA control storage means is valid, the contents of the second DMA control storage means are transferred to the third DMA control storage means. DMA transfer means having a DMA control storage means and a control means for subsequently transferring the contents of the first DMA control storage means to a second DMA control storage means and issuing the state save instruction signal. A microcomputer featuring: 7. The apparatus according to claim 6, further comprising a first bus for the central processing means to perform data processing, and a second bus for the DMA transfer means to perform DMA transfer. microcomputer.