JPH02284253A - Data transfer device - Google Patents

Abstract

PURPOSE:To efficiently execute data transfer by providing a control part to execute the mutual data transfer among a main memory and plural I/O memories between a high speed bus and a low speed bus. CONSTITUTION:In the case of the data transfer from the main memory 2 of 32-bit width to the I/O memory 9 of 16-bit width, the data transfer control device 3 reads the data of 4-bytes out of a source address (main memory), and takes it once in a data register in the data transfer control device 3, and releases a bus. After that, the source address is updated into the next address. On the contrary, in the case of the data transfer from the I/O memory 9 of 16-bits to the 32-bits main memory 2, after the data of 4-bytes is prepared by accessing the data of 2-bytes two times from the I/O memory 9, the data is written in the main memory 2. Thus, the data transfer can be efficiently executed while suppressing the fall of the throughput of a main memory bus and a CPU.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to data transfer between memories in a computer system, and particularly relates to a main memory having a high-speed bus with a large memory bus width and a low-speed main memory with a small width memory bus. The present invention relates to a data transfer device between I/O memories having a bus.

[Conventional technology]

As a conventional technology simply related to data transfer between memories, for example, direct memory access (hereinafter referred to as D
(abbreviated as MA) A device that facilitates DMA control between buses by using a DMA control circuit that outputs two sets of address data to the same signal line in time series to a control device;

As described in Japanese Patent Application Laid-open No. 63-03351, it is possible to transfer one word between storage devices in one machine cycle by accessing two storage devices with different addresses, a transfer source and a transfer destination. There are circuits that enable high-speed processing of large amounts of data.

However, as microprocessors have become faster in recent years, it has become increasingly important to improve the throughput of the memory bus between the processor and main memory, and the width of the memory bus to which the main memory is connected has increased from 16 bits to 32 bits to 32 bits. Since then, it has been expanded to 64 bits. On the other hand, various I/Os connected to the computer system are
It is desirable to be able to use conventional inexpensive hardware; for example, one
A method for connecting ■/○ with a 6-bit data width is required.

The technology described in Japanese Patent Laid-Open No. 63-98755 and Japanese Patent Laid-Open No. 63-03351 regarding direct memory access between memories mentioned above provides direct memory access between memories connected to buses with different data widths. It cannot be applied to access.

Conventional techniques for solving this problem include, for example,
As mentioned above, if the main memory data width is 32 bits and the I/O memory data width is 16 bits, by adding a simple circuit between the 32-bit bus and the 16-bit bus, the main processor's instructions can There is a method that allows access without being aware of the difference in memory.

In other words, in the case of a 32-bit data write access from the main processor to the I/O memory, this can be done using a circuit with simple hardware added to the 16-bit data.
Divide into times and write to ■/○ memory.

Further, in the case of read access, some devices read 16-bit data from the I/O memory twice and perform buffering to transfer 32-bit data.

[Problem to be solved by the invention]

Currently, memory and I/O are rapidly improving in processor performance.
The performance of the bus cannot keep up, and the performance imbalance of the system is becoming noticeable.

That is, in the conventional technology, in a data transfer device between two memory buses having different data widths and transfer speeds,
Because the main processor's instructions (for example, MVC) transfer a large amount of data to the main memory, the throughput of the CPU and bus decreases, which becomes a bottleneck in improving system performance.

This good fortune is particularly important because the memory accessed by the microprocessor in the input/output control mechanism can be accessed by the main processor within the address space of the main processor, and data transfer is performed by instructions from the main processor.
This becomes noticeable when connecting O memory.

For example, in the conventional data transfer device using the above-mentioned simple hardware-added circuit, in both write and read cases, the main processor does not access the memory until two memory accesses on the 16-bit bus are completed. During this period, the bus right of the main memory bus continues to be occupied. At this time, if the I/O memory is cheap, its access speed is usually slow, and waiting time occurs to avoid access contention with the microprocessor attached to the I/O memory. In some cases, the waiting time may be more than /O times the main memory access time. Therefore, access to the I/O memory from the main processor results in a reduction in main memory bus throughput.

Writing control data to I/O memory and reading status data in T/○ memory is at most a few bytes and does not occur frequently, so it has little impact on system performance, but it does not affect main memory and When a large amount of data is transferred between memories, a drop in throughput on the main memory bus becomes a major problem, which not only causes a drop in CPU throughput performance, but also requires high throughput for magnetic displays, etc. Engineering/○Memory DM
A may cause a problem such as overrun.

As mentioned above, in the conventional technology, when transferring data between memories with different data widths and access times,
There were problems such as a large negative impact on the throughput of the main memory bus.

In order to solve this problem, the data transfer between the main memory and the nephew I/O memory should be made independent of the main processor, realized by direct memory access between the memories, and low-speed bus access can be used to gain bus control over the high-speed bus. It is necessary to control the area so that it does not monopolize the area.

The purpose of the present invention is to solve the problems of these conventional techniques, and to provide a main memory with a large data width and a fast access time.
Data transfer between I/O memories with small data widths and slow access times can be performed efficiently without reducing the throughput of the main memory bus and by suppressing the decline in CPU throughput, improving system performance. An object of the present invention is to provide a data transfer device that improves the performance.

[Means to solve the problem]

In order to achieve the above object, the data transfer device of the present invention includes:
It has two buses with different data widths and data transfer speeds; the high-speed bus with large data width and high transfer speed uses high-speed main memory, and the low-speed bus with small data width and low transfer speed uses low-speed I/O memory. In a system in which multiple processors are connected, and both the I/O memory and the main memory are accessible from the main processor connected to a high-speed bus.

A control unit is provided between the high-speed bus and the low-speed bus to execute data transfer between the main memory and the plurality of I/O memories by accessing both memories under the control of a built-in microprogram. .

[Effect]

The data transfer device according to the present invention is interposed between a high-speed bus and a low-speed bus, and under the control of a built-in microprogram, transfers information from both buses to main memory and process/O memory connected to each bus. Can be accessed.

In the case of transfer in which the data widths of both memories are different1, for example, from a 32-bit wide main memory to a 16-bit wide I
/O When transferring data to memory, read 4 bytes of data from the source address (main memory), and then
The data is loaded into a data register in the data transfer device, thereby relinquishing the bus right to the high-speed memory and releasing the bus.

The source address is then updated to the next address.

Contrary to the above, when transferring data from 16-bit I/O memory to 32-bit main memory, access 2-byte data from I/O memory twice to create 4-byte data, and then Executes writing to main memory.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to one drawing.

FIG. 1 is a block diagram showing the configuration of a system implementing the present invention.

Main processor 1. Main memory 2, data transfer device 3 according to the invention, bus control device 8. I/O memory9. D
MAl/O/O. It consists of a 16-bit data bus 11 and a 32-bit high-speed data bus 12.

The data transfer device 3, together with the bus control device 8, has a 16-bit data bus 11 and a 32-bit high-speed data bus 12.
connected to.

Data transfer between the main memory 2 and the I/O memory 9, in which various combinations are possible, is executed by the data transfer device 3.

For example, in the case of data transfer from 32-bit wide main memory to 16-bit wide I/O memory, 4 bytes of data are read from the source address (main memory) and -
The data is then taken into the data register in the data transfer device. As a result, the bus right to the high-speed memory is relinquished and the bus is released.

The source address is then updated to the next address.

Next, in order to write this data to a 16-bit wide I/O memory, the upper 2 bytes are selected by an aligner or shifter in the data transfer device and written to the destination address of the low-speed memory.

After updating the destination address, write the lower 2 bytes to the next address, transfer byte count - 4
By doing this, the operation is completed.The operation is repeated until 6 becomes 0''.

These series of operations are complex to perform with hardwired logic, but are easy to perform under microprogram control.

Contrary to the above, when transferring data from 16-bit ■/○ memory to 32-bit main memory, access 2-byte data from I/O memory twice, create 4-byte data, and then Executes writing to main memory.

During this time, updates of the source address, destination address, and transfer byte count are the same as above.

In this way, various combinations of data transfer between memory connected to a high-speed bus with a large data width and memory connected to a low-speed bus with a small data width can be performed independently of the main processor, It is possible to improve the processing capacity of the main processor. Furthermore, the time taken to occupy the bus right of the high-speed bus for data transfer is not affected by the access time of the memory connected to the low-speed bus, and can be minimized, reducing the throughput of the high-speed bus. This makes it possible to avoid this problem and has a significant effect on improving system performance.

Further, in data transfer between memories, there is a problem of address misalignment. That is, if the lower two bits of the start address of the transfer destination and transfer source are different, multiple words (the number of bytes of the access width) of the transfer source are combined,
Although it is possible to create software that systematically prohibits one word at the transfer destination, the present invention allows such misalignment processing to be handled relatively easily under microprogram control. It is.

FIG. 2 is a block diagram showing details of the data transfer device 3 in FIG. 1.

A microprogram is stored in the ROM30.

Data is read out according to the address of the microprogram counter 32 and stored in the microdata register 31. Sequence control of the microprogram is performed by the microsequence control section 34. The microinstruction read into the microdata register 31 is decoded by the decoder 35, and the microinstruction is read out from various registers.
light.

and controls the arithmetic unit ALU48.

The 32-bit data bus 12 includes a data line MDT (32
~0-P) 66, address line MADR (31-2-P)
68. The input/output driver 59 is controlled by various bus control lines 69.
, 60, 61, and 62, and bus timing control is controlled by a 32-bit bus controller 63.

The 16-bit data bus 11 includes data lines DT (15 to
0-P)70. Address line ADR (27-1-P) 71
．． By various bus control 1%72, input/output driver 43,
Connected via 44.45.

Bus timing control is controlled by a 16-bit bus controller 42.

Register MMAR46 stores an access address to main memory 2, and register MMDR(0)56 stores read data. Register MMD
The data in R(0) 56 is shifted into register MMDR(1) 57 when newly written. As a result, 8 bytes on continuous main memory 2 are transferred to MMDR.
It can be held in (0) 56 and MMDR (1) 57.

Write data to the main memory 2 is stored in the MMBW 51 .

The aligner 52 can output any consecutive 4 bytes from the 8 consecutive bytes of register MMDR(1) 57 and register MMDR(0) 56(7). 8
Which byte to output is determined by aligner control data stored in the MALNC 53.

The main processor 1 can read and write some of the control registers in the data transfer device 3 by an input/output command, and the register CTR54 and register ADR55 can be written by the main processor input/output command. .

− is possible.

Register CTR54 is a control register, and is used when the main processor transfers data in the memory. Register CTR54 can be reset by a microprogram.

The register ADR55 is written with an address in the main memory 2 where parameters necessary for data transfer of the memory are stored.

Register 5TR58 is a status register and is used to indicate the end of data transfer and internal status.The bit that indicates the end of data transfer is the interrupt signal INT.
67, and can interrupt the main processor 1.

Register MAR41 stores an access address to I/O memory 9 connected to 16-bit data bus 11.

Register MDR (0) 38 is a register that stores the read data, and the data of register MDR (0) 38 is Frt, <-z When read, register MDR
(1)37 and is shifted into register MDR(1)3
7 data can be held in the 6 bytes on register MDR(2)36 in MDR(0)38 to MDR(2)36.

The MBW 49 stores write data to the I/O memory 9.

The aligner 39 has MDR (2) 36. MDR(1)37
, MDR(0)38(7) Any 4 consecutive bytes can be output from the 6 consecutive bytes.

ALNC determines which 4 bytes out of 6 bytes to output.
According to the aligner control data stored in 40.

In addition to the above, a WK register 50 and a register file 47 are connected to the ALU 48.

The microinstruction is divided into fields as shown in FIG. 3, and has the following functions.

F part 3/O specifies the function of ALU48.

The A section 311 specifies the A input source of the ALU 48.

The eighth section 312 specifies the B input source of the ALU 48.

D section 3.13 specifies the write register.

The MC section 314 is a main control section.

Specify the access method to the main memory 2 and I/O memory 9. The details are shown in Figure 5, and MRW 314
a specifies reading and writing to main memory 2, and MB
E314b specifies which byte position of the 4 bytes to be written to the main memory 2. MW3
14c specifies waiting for completion of access to main memory 2, RW314d specifies reading and writing to I/O memory 9, BE314e specifies writing to I/O memory 9 2
Specify which byte to write, and write W3
14f specifies waiting for completion of access to the I/O memory 9.

The LT unit 315 specifies an 8-bit literal value, extends '0' to the upper 24 bits, and sends it to the arbitrary byte shifter 33.
It can be used as a source for the B input side of the ALU 48 through the ALU 48.

The 80 section 316 specifies micro sequence control and specifies micro unconditional branches and conditional branches.

Specify the dress.

Regarding data transfer using the above data transfer device 3,
A specific example will be explained below.

The program of the main processor 1 in FIG. 1 sends an input/output command to the data transfer device 3 to read the register 5TR58 and after confirming that it is not in a busy state, the main memory 2 stores the data transfer parameters in the register ADR55. Write the address above. At this time, parameters as shown in FIG. 4 are prepared in advance on the main memory 2. That is, register ADR: 15
The 4 bytes starting from the address indicated by are the memory address 201 that will be the source of the transfer data, the next 4 bytes are the destination address 202 of the transfer data, and the next 4 bytes are a byte indicating the number of bytes of data to be transferred. A count 203 is stored.

Next, in the same manner, a command instructing the start of data transfer is written into the register CTR54.

The microprogram 3o of the data transfer device 3 reads the CTR 54 during idle and monitors whether a command is written from the main processor 1. Then, when the startup command is written, register 5TR5
After immediately turning ON the bit indicating the busy state in 8, the data in the register ADR55 is set in the register MMAR46, and the data transfer parameters are read from the main memory 2.

The read address can be easily updated using the ALU 48, and the read data is temporarily stored in the register file 47.

The memory address space allocation of this system is (00
000000)□6～(FIEFFFFFFF)0. is the main memory space, (FFOOOOOOOO), , ~(FF
FFFFFF), , are the I/O address space, and the memory 9 under the 16-bit data bus decodes the lower 28 bits.

The microprogram can determine whether the source address 201 and the destination address 202 are the main memo, based on the address values, and can determine the data transfer method. That is, (a) from main memory 2 to main memory 2, (b) from main memory 2 to ■/○ memory 9
(c) From I/O memory 9 to main memory 2.

(d) From the I/O memory 9 to the I/O memory 9, two or more four ways are possible, and the processing branches to each one.

Cases (b) and (C), which are the main focus of the present invention, will be explained in more detail.

(b) In the case of transfer from main memory 2 to I/O memory 9, source address 201 is transferred to register MM.
AR46 sets the destination address 202 in register MAR41.

Source address 201 and destination address 2
The value of the lower 2 bits and 1 bit of each address 02 is checked, the byte alignment state of the address is checked, and the value of the MALNC 53 is determined so as to control the aligner 52 so as to transfer data most efficiently. Next, start reading from main memory 2 and transfer the data to register MM.
Import into DR(0)56. At the time of import, bus ownership of the 32-bit data bus 12 is relinquished, and the main processor 1 is ready for operation. Register MMDR (
0) Output the necessary 2 bytes of the 4-byte data of 56 to the lower 2 bytes by the aligner 52, transfer it to the MBW 49, start writing to the t/O memory 9, and complete the 2-byte data transfer. .

From main memory 2 for the next 2 byte transfer.

If the next 4 bytes are needed, register MMAR46
The value of is updated by +4, and the new data is read from main memory 2 and taken into register MMDR(0) 56. At this time, the original data in register MMDR(0) 56 is shifted to register MMDR(1) 57. MALNC
After resetting the value of 53, setting the next 2 bytes to MBW49, and adding 2 to register MAR41, the I/O memory 9
Start writing to and complete the transfer of the next 2 bytes.

Executes the transfer byte force stored in the register file.

Depending on the byte alignment status of the transfer destination, care must be taken when writing at the start and end of data transfer, so that only the necessary bytes are written. This is the first
It is not a difficult process if you have the functions shown in the figure.

When the data transfer is completed, register CTR54 is reset and the end bit in register 5TR58 is turned on.

If any abnormality occurs during data transfer, that information is also reflected in the register 5TR58.

The end bit is connected to the INT line 67 and generates an interrupt to the main processor 1.

The program of the main processor 1 can wait for one interrupt after starting the data transfer and wait for the end, or it can wait for the end bit to be '1' while reading the register STR58 with an input/output command in the interrupt disabled state. You can watch and wait until it happens. After checking the contents, a command instructing a status reset is written to the register CTR54.

The microtubular program of the data transfer device 3 reads and monitors the register CTR54, and when it recognizes the status reset command, resets the register CTR54 and clears the register 5TR58 by /O'. This makes it possible to accept the next data transfer command.

(In the case of transfer from cH/○ memory 9 to main memory 2, the source address is transferred to register MAR41,
Set the destination address in register MMAR46. From both address values, the value of ALNC 40 is determined and set in order to effectively operate aligner 39. Starts reading from I/O memory 9 and registers MA
Import into R(0)38. Depending on the status of the byte aligner, read is started while register MAR41 is +2 for the required number of bytes, register MDR (, 0) 38 degrees, register MDR (1) 37. Register MDR (2) 36
, output the necessary 4 bytes from the aligner, and
The data is transferred to the BW 51 and writing to the main memory 2 is started. The transfer byte counts in register MAR46, register MMAR41, and register file 47 are updated, and similar operations are continued until the byte count becomes 0'. Depending on the byte alignment status of the transfer destination address, writing at the start and end of transfer is controlled so that only necessary byte positions are written. The processing after the end of data transfer is the same as in (b).

In either case, it can be seen that the time required to use the 32-bit data bus 12 for data transfer is minimal and does not depend on the access time of the 16-bit data bus 11.

In this way, according to this embodiment, various combinations of data transfer between memories connected to a high-speed bus with a large data width and memories connected to a low-speed bus with a small data width can be performed independently of the main processor. It is executable and can improve the processing performance of the main processor.

Furthermore, the time for occupying the bus right of the high-speed bus for data transfer can be minimized without being affected by the access time of the memory connected to the low-speed bus. This has a significant effect on improving system performance.

In addition, in this embodiment, explanation was given regarding control by a microprogram, but PLA (Program
It is also possible to realize the control using a main memory 2 (mable logic array).Furthermore, although the explanation of data transfer within the main memory 2 has been omitted, the method is easily understood from the above explanation. Transferring a large amount of data within is very effective for controlling RAM disks and memory residency of files.

Although the amount of hardware required by the present invention is relatively large, considering the recent improvements in LS II integration, this is not a major problem. is quite possible.

〔Effect of the invention〕

According to the present invention, data transfer in various combinations between a memory with a large data width and a fast access time and a memory with a small data width and a slow access time can be performed without reducing the throughput of the main memory bus. , and CP
It suppresses the drop in U throughput and enables efficient operation, and also enables data transfer between memories and transfer when there is an address misalignment between transfer addresses, which has a significant effect on improving system performance. It is.

Furthermore, in order to reduce the cost of the entire system, the number of cases in which memory is layered and high-speed memory and low-speed memory are connected using adapters is expected to increase. In such cases, the present invention becomes important as a technique for using low-speed memory without reducing the throughput of the high-speed bus or CPU.

In addition, due to the improvement in LSI integration in recent years, ordinary DMA
It is possible to incorporate the data transfer mechanism of the present invention in the same chip as the controller, and it is also possible to apply it to a RAM disk, etc., and the CPU 22:, 23:,
24:, 25:, 26:, 27:.

RAM disk and memory files that reduce the burden on 2
8:, 29:, 30: ROM (It is possible to realize microprogramming. RAM)
, 31: Micro data register, 32: 4, Brief explanation of the drawings: Micro program counter, 33: Arbitrary byte The drawings show an embodiment of the present invention, and FIG. :Block diagram showing the configuration of the system, 2nd decoder, 36: register M
DR(2), 37: The figure shows details of the data transfer device 3 in FIG. 1. Register MDR(1), 38: Register designation R(0).

Figure 3 shows the data transfer in Figure 1.
9 near liner, 40: ALNC, 41 near liner feeding device 3
indicates the field division of the microinstruction of TAMAR,
42: 16 bits 1~bus control section, 43~da configuration diagram, 4th
The figure shows the main memory in FIG. 1. 45: Input/output driver, 46: Register MMAR.

A configuration diagram of parameters prepared in advance in 2,
47: Register file, 48: Arithmetic unit ALU.

Figure 5 shows the method 4 of the microinstructions in Figure 3.
9: MBW (storage of structure indicating details of write-in control unit MC unit 314 to I/O memory 9), 50: WK register, 51: MMBW configuration. (Storage of write data to main memory 2).

1: Main processor, 2: Main memory, 3:
52 Near aligner, 53: MALNC (aligner-based data transfer device, 4:, 5:, 6:, 7:, 8: storage of control data), 54: Register CTR, 55: Bus control device, 9: I/O memory , /O: DMA register ADR, 56: register MMDR (0).

■/O, 11:16 bit data bus, 12:32
57: Register MMDR (1), 58: Register bit high-speed data bus, 13:, 14:, 15:,
STR, 59-62: Input/output driver, 63: 3216
:, 17:, 18:, 19:, 20:, 21:, - head bus control section, 64-65: logic gate, 66: data line MDT (32-0-P), 67: interrupt signal TNT,
68 Near address line MADR (31 to 2-P), 69: Various bus control lines (32 bits), 70: Data line DT (1
5~0-P), 71 near address line ADR (27~1-P)
), 72: Various bus control lines (16 bits), 201: Memory address (source of transfer data), 202: Destination address of transfer data, 203: Byte count (indicates the number of bytes of transfer data), 3/O : Micro program F section (ALU48 function specification), 311: Micro program A section (ALU48 function specification)
6-input source specification), 312: Microprogram 8
(B input source specification of ALtJ48).

313; Microprogram 0 section (write register specification), 314: Microprogram MC section (main control section), 314a: MRW (read/write specification to main memory 2), 314b: MBE (write to main memory 2) Byte position specification), 314c
:~tW (Specification of waiting for completion of access to main memory 2)
, 314d: RW (read/write specification to 1/○ memory 9), 314e: BE (write byte specification to I/O memory 9), 314f:W (I/O memory 9
(Specification of waiting for access to end).

315: LT section (literal value specification), 316: SC section (micro sequence control specification), 317: BA section (
Specifying the branch address of the microprogram).

No. figure No. figure

Claims (1)

[Claims] 1. It has two buses with different data widths and data transfer speeds, the high-speed bus with a large data width and high transmission speed has a high-speed main memory, and the low-speed bus with a small data width and a low transfer speed has a low-speed I/O bus. Multiple O memories are connected, and the I
In a system in which both the /O memory and the main memory can be accessed from a main processor connected to the high-speed bus, between the high-speed bus and the low-speed bus, the main memory and the plurality of I/O memories are A data transfer device comprising a control means for accessing both memories and executing data transfer under the control of a built-in microprogram.